CODEWITHSUNDEEP
vhdlfpgaxilinx
psfpga
psfpga

Reputation: 3

Error with VHDL integer signal connecting Verilog integer input

I trying to connect VHDL module's output integer port to signal. And this signal will connect other module. (This module wrote in Verilog). But I encounter this

ERROR : VHDL integer data type not supported for actual signals in component instantiation across language boundaries. Port "fifo4_frame_number" is an integer VHDL signal connected to a Verilog port.

I must also say that i can generate bitstream. there is no problem.

Upvotes: 0

Views: 792

Answers (2)

Matthew
Matthew

Reputation: 13987

An integer in VHDL is fundamentally different to an integer in Verilog, so it is no surprise that they are not compatible. The integer type in VHDL is like an integer type in any other language, whereas the integer type in Verilog is just short hand for a vector. This

integer i;

and this

reg signed [31:0] i;

are exactly equivalent in Verilog. As others have said, you need to convert to std_logic_vector in VHDL.

Upvotes: 1

snus74
snus74

Reputation: 451

You must convert the integer to logic_vector in your VHDL file such that the ports have the same type. Ports cannot be of integer type across both languages

Upvotes: 0

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