CODEWITHSUNDEEP
system-verilog
bu-ral
bu-ral

Reputation: 431

How to pass interface modport signal into other module?

I'm trying to implement an interface with modports. I have 2 modules inside a testbench.

module test;
test_intf intf();

clk_reset u_clk_reset (
            intf.CLK_RESET
                );

mem u_mem(
        intf.MEM
    );
....
endmodule

This is the interface:

interface test_intf;
logic reset_n;
logic aclk;
logic bclk;
logic areset_n;

logic               wr_in;
logic               rd_en;
logic    [ 9:0]     wr_addr;
logic    [23:0]     wr_data;
logic    [ 9:0]     rd_addr;
logic     [23:0]    rd_data;

modport CLK_RESET (output aclk, bclk, areset_n);
modport MEM (output rd_data, input clk, reset_n, wr_in, rd_en, wr_addr, wr_data, rd_addr);

endinterface

This is the clk_reset module:

module clk_reset(
test_intf intf
);


always #(5) intf.aclk = ~intf.aclk;
initial begin
 intf.aclk = 0;
end

initial begin
 intf.areset_n = 1;
 #2000  intf.areset_n = 0;
 #2000  intf.areset_n = 1;
end

This is the mem module:

module mem
        (
test_intf intf
);

always @(posedge intf.clk or negedge intf.reset_n)
begin
    //end
end

I checked that the clk_reset interface ports are working (all outputs). But, the problem is that the output clock signals from clk_reset can't reach the mem module by interface. So, intf.clk signal is 'x' in the mem module.

How do I pass some interface's signals into another interface (module)?

Upvotes: 1

Views: 633

Answers (1)

toolic
toolic

Reputation: 62037

Your simulator should have given you a compile error. The interface is missing the declaration of the clk signal. Add it like this:

logic clk;

Since you want to use clk inside mem, you need to add clk to the CLK_RESET modport list:

modport CLK_RESET (output aclk, bclk, clk, areset_n);

Finally, you need to generate the clk signal so that it is not X. Here are the required changes:

interface test_intf;
    logic reset_n;
    logic aclk;
    logic bclk;
    logic clk;
    logic areset_n;

    logic               wr_in;
    logic               rd_en;
    logic    [ 9:0]     wr_addr;
    logic    [23:0]     wr_data;
    logic    [ 9:0]     rd_addr;
    logic     [23:0]    rd_data;

    modport CLK_RESET (output aclk, bclk, clk, areset_n);
    modport MEM (output rd_data, input clk, reset_n, wr_in, rd_en, wr_addr, wr_data, rd_addr);
endinterface

module clk_reset(
    test_intf intf
    );

    always #(5) intf.aclk = ~intf.aclk;
    initial begin
     intf.aclk = 0;
    end

    always #(5) intf.clk = ~intf.clk;
    initial begin
     intf.clk = 0;
    end

    initial begin
     intf.areset_n = 1;
     #2000  intf.areset_n = 0;
     #2000  intf.areset_n = 1;
    end
endmodule

Upvotes: 1

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