CODEWITHSUNDEEP
verilog
Raphael
Raphael

Reputation: 1001

Force internal signal of a module - Verilog

I have a verilog testbench in order to perform gate level simulation of a module. I want to inject a transient voltage at the output of specific gates inside the module but can't find a way to do it. I can insert transient voltages (like glitches) at the inputs (example below), but I need to inject on internal signals. Can anyone shed a light on the issue?

Example: glitch in a clock signal (source)

always begin: inject_clk_glitch
    #1 force clk = 1;
    #1 force clk = 0;
    #1 release clk;
end

Upvotes: 0

Views: 6475

Answers (2)

Joniale
Joniale

Reputation: 595

In case you are using other vendor like Synopsys and you want to force from systemverilog to VHDL, then you would like to use the $hdl_xmr_force vendor function. In case of a boolean type then you will have to convert manually to TRUE/FALSE. Questa does not have that limitation i think.

You can add a task in your systemverilog interface or in your module and use a hierarchy to force/release your signals.

task force_deposit_output_sr_update( bit value=0);
`ifdef VCS
    if (value==0) begin
    $hdl_xmr_force("DUT.U01.U06.U02.U_USE_U03.U03.U01.UPDATE_SR_OUTPUT", "FALSE", "0 ps", "deposit",  , 0);
    end else begin
    $hdl_xmr_force("DUT.U01.U06.U02.U_USE_U03.U03.U01.UPDATE_SR_OUTPUT", "TRUE", "0 ps", "deposit",  , 0);
    end
`else
   //QUESTA
    force DUT.U01.U06.U02.U_USE_U03.U03.U01.UPDATE_SR_OUTPUT = value;//direct force DUT intern signal
 `endif
endtask

task force_deposit_output_change(logic[31:0]  value='hABCDABCD);
`ifdef VCS
    $hdl_xmr_force("dut.U01.U06.U02.U_USE_U03.U03.SYNC_OUTPUT", "value", "0 ps", "deposit",  , 0);
`endif
endtask

Upvotes: 1

dave_59
dave_59

Reputation: 42698

force DUT.internal_path.internal_signal = 1;

Upvotes: 2

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