CODEWITHSUNDEEP
verilogsystem-verilogfpgavivado
jackpanderson
jackpanderson

Reputation: 11

Widening an array in SystemVerilog?

For a digital design class, I am designing a 4-bit adder using an FPGA board. To add subtraction functionality, our professor suggested to convert our 4-bit input (represented as an array) to a 6-bit input. I am trying to write a simple module that takes in a 4-bit array and outputs a 6-bit array with the same values at indices 0-3, and have values at indices 4 and 5 to be zero, but I cannot figure out why this keeps breaking my simulations. My 4 bit adder was functional before I added the 4 -> 6 bit converter. Is there just something obvious I'm missing here?

module bus_widener(input [3:0] in, output reg [5:0] out);
    assign out[0] = in[0];
    assign out[1] = in[1];
    assign out[2] = in[2];
    assign out[3] = in[3];
    assign out[4] = 1'b0;
    assign out[5] = 1'b0;
endmodule

I have tried using a case statement with an always true case, smaller modules within this that copied one bit to another, and nothing has worked.

Upvotes: 1

Views: 151

Answers (1)

toolic
toolic

Reputation: 62163

Perhaps your simulator does not have SystemVerilog features enabled, and it is unhappy with continuous assignments (using the assign keyword) to a reg.

Change:

module bus_widener(input [3:0] in, output reg [5:0] out);

to:

module bus_widener(input [3:0] in, output [5:0] out);

Also, a simpler way to code this is to use concatenation:

module bus_widener (input [3:0] in, output [5:0] out);
    assign out = {2'b00, in};
endmodule

Upvotes: 1

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