CODEWITHSUNDEEP
verilogsystem-verilog
Jean
Jean

Reputation: 22715

How do you escape % in SystemVerilog?

How do you escape % in the SystemVerilog $display statement?

Upvotes: 2

Views: 821

Answers (1)

toolic
toolic

Reputation: 62121

From IEEE Std 1800-2017, section 21.2.1 The display and write tasks:

The special character string %% indicates the display of the percent sign character %

module tb;
    initial $display("hello %% world");
endmodule

The above displays:

hello % world

Run it on EDA playground.

For a more complex example, see How can I automatically scale a $display column width?

Upvotes: 3

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