adieux
adieux

Reputation: 66

How to do Verilog variable part select with % on both sides of colon?

I understand that for variable part select, there can't be a variable on both sides of the colon:

a_vect[ 8*i +: 8] // == a_vect[(8*i+7) : 8*i]

However, I need to convert this code:

a_vect[(i*16+3)%64 : (i*16)%64]

How do I deal with the "%64" on both sides of the colon?

Upvotes: 1

Views: 833

Answers (3)

Rama Krishna Meda
Rama Krishna Meda

Reputation: 363

a_vect[(i*16+3)%64 : (i*16)%64]

when elaborated

i=0 ==> a_vect[3:0]
i=1 ==> a_vect[19:16]
i=2 ==> a_vect[35:32]
i=3 ==> a_vect[51:48]
i=4 ==> a_vect[3:0]

u can use this type

  for(genvar i=0;i<64;i+16)
        a_vect[i+:4]

Upvotes: 0

acmert
acmert

Reputation: 129

Alternatively, you can use shift operation:

temp = (a_vect >> ((i*16)%64));

If temp variable is not defined as 4-bit, use:

temp = (a_vect >> ((i*16)%64)) & 4'hF;

Upvotes: 1

Justin N
Justin N

Reputation: 911

The +3 won't cause the mod to wrap, so just remove it:

a_vect[(i*16)%64 +: 4]

(If it did, the original code wouldn't work anyway.)

Upvotes: 2

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