CODEWITHSUNDEEP
verilogsystem-verilogfpga
Eliza
Eliza

Reputation: 1

Trying to find Verilog Version of $realtime (SystemVerilog function)?

I'm trying to rewrite some Verilog files to be implemented on an FPGA. This means that I need to rewrite some SystemVerilog as Verilog so it can be synthesized.

The code I'm using has realtime net types and calls the function $realtime and I have no clue how to rewrite it to be regular Verilog. A snippet of this code can be seen below:

realtime t_pad_current_transition,t_pad_prev_transition;
realtime t_filt_in_h_current_transition,t_filt_in_h_prev_transition;
realtime pad_pulse_width, filt_in_h_pulse_width;
always @(PAD)
begin
    if (^PAD !== 1'bx)
    begin
        t_pad_prev_transition       = t_pad_current_transition;
        t_pad_current_transition    = $realtime;
        pad_pulse_width             = t_pad_current_transition - t_pad_prev_transition;
    end
    else
    begin
        t_pad_prev_transition       = 0;
        t_pad_current_transition    = 0;
        pad_pulse_width         = 0;
    end
end

I've thought about changing them to registers, but that still doesn't fix the issue of the $realtime line.

Upvotes: 0

Views: 479

Answers (1)

dave_59
dave_59

Reputation: 42738

This code is in Verilog already. It is not synthesizable.

realtime is just a synonym for real. real is not synthesizable.

if (^PAD !== 1'bx) is not synthesizable.

$realtime is not synthesizable

Upvotes: 1

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