CODEWITHSUNDEEP
verilogice40
zapta
zapta

Reputation: 125

How to reset the RTL on power up for the Lattice ICE40 FPGA?

I am designing for the ICE40 using Verilog, looking for a signal to be used as reset on power up.

Does the ICE40 provide a specifically built-in power on reset (POR) signal or do I need to implement it myself, e.g. with some counter or delay?

If I implement a state machine to generate the power reset, how to I reset it on power up without a POR signal? Kind of a chicken and an egg.

The board I am using: Upduino3 The FPGA it uses: ICE40UP5K-SG48ITR

Toolchain: APIO cli

Upvotes: 0

Views: 443

Answers (1)

Mikef
Mikef

Reputation: 2508

The board does not have a physical push button reset.
There is a poor man's voltage monitor/power on reset (called CRESET_N on the schematic) for the FPGA configuration only; it does not propagate into the FPGA fabric (no Verilog RTL access to this). Its just a pull up resistor.

The very short answer to the chicken/egg problem is that the flops start out at 0 after configuration due to a built-in reset.

Others have asked/answered here github.
There are several there, this one is concise:

"The lattice chips don't have support for initial values on registers. They are cleared on startup and reset. There is little the tools can do to fix this, so you need to route an initialization signal as far as I know. I usually do something like this:"

  reg ready = 0
   always @(posedge clk) begin
      if (ready)
        <run>
      else begin
        <initialize>
        ready = 1
      end
  end

Recommend that you follow the other links to understand the various ideas presented at the link.

The FPGA datasheet maybe there is a better place to access it is somewhat helpful re reset and has this quote.

"A D-style Flip-Flop (DFF), with an optional clock-enable and reset control input, builds sequential logic functions. Each DFF also connects to a global reset signal that is automatically asserted immediately following device configuration."

Its nice when the board has at least one or more push button(s) switchs connected to a FPGA GPIO for stuff like this. The board looks tiny in this case though so maybe there was no room for a push button.

Upvotes: 2

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