CODEWITHSUNDEEP
verilogfpgalatticehdlice40
TinLethax
TinLethax

Reputation: 11

Cascading BRAM in iCE40 FPGA

I'm really new to FPGA and Verilog. I've been working on the Tri-SPI PHY controlling Noritake Itron VFD Display. One of the feature I want to implement is the framebuffer memory on the FPGA itself. I'm using the iCE40LP1K which has 64kbit BRAM (8Kbytes). But the Verilog BRAM Primitive is 4kbit and I required 3003 bytes for buffer.

The question is how can I cascade the BRAM ? in the datasheet (refer to iCE40 LP/HX Family Data Sheet, page 2-6) mentioned about using multiple BRAM. Is there a way that I can use multiple instance of SB_RAM40_4K? and the later treat as a one large mem array.

Upvotes: 0

Views: 818

Answers (2)

TinLethax
TinLethax

Reputation: 11

I be able to successfully use the BRAM as I wanted. It turns out that I just declare the register as 8bit array. And just make sure that there're input and output to/from that register array. Since I need 3004 bytes, this code below is how I make it work: (Note: names aren't important, Yosys is smart enough to map to SB_RAM40_4k. Also you change the array size and address bit width).

module BRAM(
input R_CLK,
input W_CLK,

input [7:0]BRAM_IN,
output reg [7:0]BRAM_OUT,

input [11:0] BRAM_ADDR_R,
input [11:0] BRAM_ADDR_W,

input B_CE_W,
input B_CE_R);

reg [7:0] mem [3003:0];

always@(posedge R_CLK) begin// reading from RAM sync with system clock 
if(!B_CE_R)
    BRAM_OUT <= mem[BRAM_ADDR_R];   
end 

always@(posedge W_CLK) begin// writing to RAM sync with Slave SPI clock.
if(!B_CE_W)
    mem[BRAM_ADDR_W] <= BRAM_IN;
end

endmodule

Upvotes: 0

Vlad
Vlad

Reputation: 5857

Typically you would use some tools from the manufacturer of your FPGA. It's very common (probably even granted) that you have some wizard that will instantiate the IP you need.

In such wizard/editor/generator you will select the type of the memory you need (single/dual ported, width,depths,etc), and that tool will generate files that will instantiate required hw blocks. The wizard is responsible for doing that in the most optimal way, like stitching the blocks of ram using minimal width and maximal depth, in order to minimize the number of elements wasted on multiplexers.

Upvotes: 0

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