CODEWITHSUNDEEP
caseverilogsystem-verilogdefault
Matteo5v5
Matteo5v5

Reputation: 11

Effect on synthesis when adding default to a unique case

In System Verilog, I want to instruct the synthesizer to infer a parallel check of some conditions, thus I am using a unique case. I am also adding a default statement. What I would expect is the synthesizer to treat all my case statements, included the default, as mutually exclusive, thus inferring a parallel check of the conditions. Is that what will happen, or does the presence of the default break the parallel check?

I am asking this because the linting tool complains the unique case has a default statement, but I couldn't find an answer anywhere. I tried removing the unique keyword from a bunch of case statements in my design and perform synthesis before and after, and it yields exactly the same area. Thus, it makes me think that the default keyword is inferring priority logic.

Upvotes: 1

Views: 121

Answers (1)

toolic
toolic

Reputation: 62236

Refer to IEEE Std 1800-2023, section 12.5.3 unique-case, unique0-case, and priority-case for a detailed description of unique case. Here is one quote:

NOTE — By specifying unique or priority, it is not necessary to code a default case to trap unexpected case values.

This might be the reason behind why the linting tool complains. The purpose of lint tools is to check for coding styles which might fall outside of recommended coding styles. Since the Std says you should not need a default, it is reasonable for the lint tool to complain. It is encouraging you to think carefully about whether you really need the default. Refer to the lint tool documentation for further details on the complaint message that you received.

The real benefit of using unique case is that the tool checks to see if any case_items overlap. If there is an overlap, the tool should generate a violation report.

Upvotes: 0

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