CODEWITHSUNDEEP
verilogsystem-verilog
zapta
zapta

Reputation: 125

Does the SystemVerilog standard allows mixing with Verilog files?

Does the SystemVerilog standard permit to mix SystemVerilog files (.sv) with Verilog files (.v)?

Upvotes: 1

Views: 55

Answers (2)

dave_59
dave_59

Reputation: 42748

SystemVerilog is 100% backward compatible with Verilog with one major exception: additional reserved keywords. This means any working code in Verilog will compile and behave the same SystemVerilog as long as the Verilog code does not use any SystemVerilog keywords like logic or bit.

SystemVerilog does provide compiler directives `` `begin/end_keywords to un-reserve those keywords regardless of any tool specific command line behavior. But most tools automatically provide that capability by looking at the extension of the file on the compilation command line.

Upvotes: 1

toolic
toolic

Reputation: 62236

The SystemVerilog standard (IEEE Std 1800-2023) does not have any rules or restrictions regarding file name extensions.

Individual software tools that compile Verilog source code files may have special treatment of the .sv and .v file extension, but this is not universal. Behavior will vary from simulator to simulator, for example. You need to refer to the documentation for your particular tool.

Upvotes: 1

Related Questions