CODEWITHSUNDEEP
chiselfirrtl
AlexMontgomerie
AlexMontgomerie

Reputation: 11

Adding an AttributeAnnotation to a SyncReadMem object in latest Chisel versions

I am trying to annotate a SyncReadMem object with with a verilog attribute in the newer versions of Chisel (>3.6.1). I'm using Chisel mostly for FPGA development, and so for the different FPGA manufacturers you can use attributes to specify the type of on-chip memory you want. Previously you could use the following with the firrtl backend:

  val ram = SyncReadMem(entries, Vec(1, gen), SyncReadMem.WriteFirst)
  annotate(new ChiselAnnotation {
    def toFirrtl = AttributeAnnotation(ram.toTarget, 
                                       f""" ram_style = "block" """)

But with the firtool-based compiler, it seems that this can't work as it throws the error:

error: firrtl.AttributeAnnotation unhandled operation. The target must be a module, wire, node or register

looking at the .fir, memory gets synthesised as smem ram : UInt<8>[1] [1024] new, which isn't one of the allowed targets. At the end of the day it does get converted to an array of registers if you elaborate to system verilog (reg [7:0] Memory[0:1023];), which is ultimately the target I'm looking for.

Is there a way of getting the target for the array of registers all the way from the SyncReadMem in Chisel?

Upvotes: 1

Views: 18

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