CODEWITHSUNDEEP

StackOverflow Questions for Tag: firrtl

AlexMontgomerie

Reputation: 11

Adding an AttributeAnnotation to a SyncReadMem object in latest Chisel versions

Score: 1

Views: 24

Answers: 0

Aperture Initiative

Reputation: 58

In Chisel3, how to add `mark_debug = "true"` attribute to an internal signal in the output SystemVerilog file?

Score: 0

Views: 53

Answers: 1

gowthamkumar dubakula

gowthamkumar dubakula

Reputation: 11

Exception in thread "main" chisel3.package$ChiselException: Unable to locate the elaborated circuit, did chisel3.stage.phases.Elaborate run correctly

chiselchiseltestfirrtl

Score: 1

Views: 203

Answers: 0

DDK

Reputation: 136

How to move sram to top hierarchy in Chisel3/Firrtl

memoryhierarchychiselsynthesizefirrtl

Score: 1

Views: 37

Answers: 0

Reputation: 239

Initializing IO with a bundle in Chisel 3.5

Score: 0

Views: 303

Answers: 1

Reputation: 1919

what is the best practice to initialize a FIRRTL memory?

Score: -1

Views: 190

Answers: 1

Reputation: 1919

what is the idiomatic way to update part of a memory element in FIRRTL? this comes up when updating one entry of a line in a cache

Score: 1

Views: 86

Answers: 1

Reputation: 1919

how to get a critical path / bottleneck analysis of FIRRTL code?

riscvchiselfirrtl

Score: 2

Views: 160

Answers: 1

Reputation: 1919

what do "cmem", "infer", and "mport" mean?

Score: 2

Views: 135

Answers: 1

Reputation: 23

False "Combinational loop detected"

scalachiselfirrtl

Score: 2

Views: 818

Answers: 1

Reputation: 11

Bundle using Mux

Score: 1

Views: 95

Answers: 1

Mokhtar H.

Reputation: 19

How to emitVerilog from Firrtl with annotations

annotationsverilogchiselfirrtl

Score: 1

Views: 164

Answers: 0

Reputation: 25

Chisel: fail to generate verilog while writing a simple combinational logic

scalaverilogchiselfirrtl

Score: 1

Views: 247

Answers: 1

Reputation: 11

Chisel 3.4.2 syncmem and a black box. No memory replacement with --repl-seq-mem option

Score: 1

Views: 304

Answers: 1

Phantom

Reputation: 185

Differences between LazyModule and LazyModuleImp

riscvchiselrocket-chipfirrtl

Score: 1

Views: 687

Answers: 1

Reputation: 177

Chisel/FIRRTL DefnameDifferentPortsException

Score: 3

Views: 240

Answers: 1

Reputation: 4051

How to convert a deprecated low Firrtl Transform to the Dependency API

Score: 2

Views: 88

Answers: 1

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