CODEWITHSUNDEEP
vhdl
SamSong
SamSong

Reputation: 69

What is this VHDL code setting max and min to? An explanation of fixed point representation would be helpful

 constant MAX      : unsigned(18 downto 0) := "100" & x"0000";
 constant MIN      : unsigned(18 downto 0) := "001" & x"0000";

What is this VHDL code setting max and min to? An explanation of fixed point representation would be helpful.

Upvotes: 0

Views: 1256

Answers (1)

simon
simon

Reputation: 1145

  • The & operator concatenates the two bit vectors "100" and x"0000" (e.g. "00" & "11" would be equivalent to "0011").
  • The X"012345689ABCDEF" syntax means that the following vector should be interpreted as a hex number (e.g. X"0" actually is "0000", X"F" would be "1111" or X"0F" would be "00001111"). This allows you to write a bit vector in a more compact way.

For the interpretation of a bit vector check e.g. http://en.wikipedia.org/wiki/Binary_numeral_system

For representation of hexdecimal numbers check e.g. http://en.wikipedia.org/wiki/Hexadecimal

Edit for clarification: I assume you are using the unsigned type from the numeric_std package. From the header of that package

This package defines numeric types and arithmetic functions
for use with synthesis tools. Two numeric types are defined:
-- > UNSIGNED: represents UNSIGNED number in vector form
-- > SIGNED: represents a SIGNED number in vector form
The base element type is type STD_LOGIC.
The leftmost bit is treated as the most significant bit.
Signed vectors are represented in two's complement form.

So your MAX is set to 2^18 and your MIN to 2^16.

Upvotes: 4

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