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parametersverilogfpgahdl
vlsi2013
vlsi2013

Reputation: 169

verilog : defining parameter values in case statement?

I need to define parameter values which are dependent on some other input . I tried the following way but it doen't work . any other alternative methods ?

 module (...)
...
input sel ;
..
case (sel)
0: parameter data1 =5;
1: parameter data1 =5;
endcase
...

Thanks

Upvotes: 0

Views: 4026

Answers (1)

Morgan
Morgan

Reputation: 20514

Parameters are constants, therefore can not be changed at runtime and will not work with dynamic structures.

If you need to set values based on inputs, which change during execution and you just need to define a wire or reg of the correct width.

Alternatively for constants you can use hierarchical parameters where you pass values down but they must all be based on parameters or constants.

module top();
  localparam DATA_WIDTH = 32;

  middle #(
    .DATA_WIDTH( DATA_WIDTH )
  ) middle_0();

endmodule

module middle #(
  parameter DATA_WIDTH = -1

  //DO NOT MODIFY
  parameter DATA_OUT_WIDTH = DATA_WIDTH + 10;
)(
  output [DATA_OUT_WIDTH-1:0] data_tx
);
endmodule

For your case:

module (...)
...
input sel ;
..
  reg [3:0] data1;
  always @*
    case (sel)
      0: data1 =5;
      1: data1 =5;
    endcase
  end

endmodule

Upvotes: 3

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