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Bob Fang
Bob Fang

Reputation: 7381

Is a <= a + 1 a good practice in VHDL?

If I write the statement to assign a to be a+1 in a VHDL process, is it a good practice?

I am confused about this because the simulator works fine, but when I try to implement it in FPGA the synthesis tool complains about creating latches.

What does this mean?

Upvotes: 2

Views: 1380

Answers (3)

Martin Thompson
Martin Thompson

Reputation: 16812

Do it in a clocked process, that's fine. What it means is "the next value of a should be the current value of a +1"

If you do it as a continuous assignment (outside of any process), what you are saying is "a is always getting a+1 assigned to it" which is a self-referential loop!

If you include a in the sensitivity list of an enabled process, you get the same effect

process (en, a)
begin
   if en = '1' then 
      a <= a + 1;
   end if;
end process;

(You can use this form to create transparent latches:

process (en, insig)
begin
   if en = '1' then 
      a <= insig;
   end if;
end process;

)

If you do it in a non-clocked process, which is not sensitive to a:

process (en)
begin
   if en = '1' then 
      a <= a + 1;
   end if;
end process;

You will create a positive-edge-triggered latch, as a needs to keep its value between changes of en. Effectively, en becomes a clock to a d-type flipflop.

Upvotes: 3

baldyHDL
baldyHDL

Reputation: 1387

you should do such a statement only in a clocked process. if you want to have it synthesised, an additional initialisation (reset) is suggested. might look as follows:

process(clk, reset)
begin
   if reset='1' then
      a <= 0;
   elsif rising_edge(clk) then
      a <= a + 1;
   end if;
end process;

Upvotes: 7

user1818839
user1818839

Reputation:

In a clocked process, this is fine. Anywhere else, probably not.

Upvotes: 5

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