CODEWITHSUNDEEP
syntaxvhdl
chromozonex
chromozonex

Reputation: 211

VHDL Syntax error in IF-ELSE block of finite state machine

IF (((SW(17) = '0') OR ((SW(17) = '1') AND (SW(16) = '0'))) OR ((SW(17) = 1) AND (SW(16) = 0) AND (SW(14) = 1)) AND (tempCounter = 1)) THEN
           next_state <= STATE1;
           resetTempCounter <= '1';
        ELSE
           next_state <= STATE0;
        END IF;

The code above throws a syntax error. I have checked the brackets, and I don't think that's the problem. I initially broke up the long line and thought that was the problem but that wasn't. I should also probably inform you that the code is in a process statement and that is not the problem.

Errors:

Error (10500): VHDL syntax error at Lab4b.vhd(241) near text "AND"; expecting ")", or ","

Error (10500): VHDL syntax error at Lab4b.vhd(244) near text "ELSE"; expecting "end", or "(", or an identifier ("else" is a reserved keyword), or a sequential statement

I'm fairly new to VHDL programming so bear with me and I would appreciate your help.

Upvotes: 0

Views: 1290

Answers (3)

user1818839
user1818839

Reputation:

Reformat the line and the problem is easier to spot...

IF (((SW(17) = '0') OR ((SW(17) = '1') AND (SW(16) = '0'))) 
 OR ((SW(17) = 1) AND (SW(16) = 0) AND (SW(14) = 1))
 AND (tempCounter = 1)) THEN

In one place, SW(17) = '0' - this is a std_logic or bit value. correct.
In another, SW(17) = 1 - this is an integer, ... not so much.

I believe that too many brackets deducts from clarity, I would reduce 

(((SW(17) = '0') OR ((SW(17) = '1') AND (SW(16) = '0'))) 
 ... )

to

((SW(17) = '0' OR (SW(17) = '1' AND SW(16) = '0')) 
 ... )

to reduce confusion a little. Who knows, with a bit less clutter you might have spotted the simple typos yourself?

Upvotes: 0

baldyHDL
baldyHDL

Reputation: 1387

let me write your statement in a different way to show the problem:

A = ((SW(17) = '0') OR ((SW(17) = '1') AND (SW(16) = '0')))
B = ((SW(17) = '1') AND (SW(16) = '0') AND (SW(14) = '1'))
C = (tempCounter = '1')

you have now:

if A or B and C then
   ...

the issue can be solved by writing e.g.:

if (A or B) and C then
   ...

or 

if A or (B and C) then
   ...

Upvotes: 0

Daniel Kamil Kozar
Daniel Kamil Kozar

Reputation: 19286

Supposing that SW is declared as a bit_vector or an STD_LOGIC_VECTOR, you've got your comparison operators wrong : remember that both bit and STD_LOGIC are really enumerated types consisting of values mimicking the "real" ones, and not integers (in which case 0 and 1 would make a valid choice).

Therefore, all that you need to do is add apostrophes around 0 and 1 in this case. Check if this works (also supposing that tempCounter is an STD_LOGIC or bit type signal) :

(((SW(17) = '0') OR ((SW(17) = '1') AND (SW(16) = '0'))) OR ((SW(17) = '1') AND (SW(16) = '0') AND (SW(14) = '1')) AND (tempCounter = '1'))

Upvotes: 0

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