Reputation: 351
I am new to VHDL. I am trying out a code to find whether a bit vector is is even r not (using hamming weight of the bit vector). The code I wrote is:
entity hw_mod is
generic(
bits:integer );
port (
inp : in std_logic_vector((bits-1) downto 0;
cout : out std_logic );
end entity hw_mod
architecture hw_arch of hw_mod is
begin
process(inp)
variable count : Integer:=0;
begin
labelloop: for i in 0 to (bits-1) loop
if(inp(i)=='1') then
count:= count+1;
end if;
end loop;
if ((count mod 2)== '0') then
cout:=1;
else
cout:=0;
end if;
end process;
end hw_arch;
the error I keep getting is "near "=": syntax error in two places.
Upvotes: 0
Views: 2037
Reputation: 3730
Several problems. Use an editor that checks your syntax while you type.
==
instead of =
) :=
instead of <=
)Upvotes: 1
Reputation: 92
I checked your code:
- the generic was not ok
- cout is a signal, so it needs <=
- :=
is only for variables
It gives no errors, but still there are latches. Variables need to be initalized before using.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity hw_mod is
generic(
bits : integer range 0 to 3 := 3);
port (
inp : in std_logic_vector((bits-1) downto 0);
cout : out std_logic );
end entity hw_mod;
architecture hw_arch of hw_mod is
begin
process(inp)
variable count : Integer:=0;
begin
labelloop:
for i in 0 to (bits-1) loop
if(inp(i)='1') then
count:= count+1;
end if;
end loop;
if ((count mod 2)= 0) then
cout <= '1';
else
cout <= '0';
end if;
end process;
end hw_arch;
Upvotes: 0