CODEWITHSUNDEEP
comparevhdlclock
d2key
d2key

Reputation: 71

compare two clock signals

we are designing a robot for my university project with a group, we are first year electrical engineering students. the robot has to detect mines with a simple LC oscillator en comparator. the output of this circuit is a block wave so that our FPGA can count up to a specified number and then compare with a pre defined number, to see if there is any change in the frequency of the oscillator (meaning that there is a metal object under the sensor). i wrote this but it seams that the rising_edge(sensor) does not work, dont understand because both counter are practically the same. the entity of the clock is exactly the same, but with the clock as input.

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.all;

entity metaal_detector is
  port(
    sensor, reset: in std_logic;
    sensor_out: out std_logic_vector(10 downto 0)
 );
 end entity metaal_detector;

 architecture behavioural of metaal_detector is
signal  count, new_count    : unsigned (10 downto 0);

begin
process (sensor)
begin
    if (rising_edge (sensor)) then
        if (reset = '1') then
            count   <= (others => '0'); -- zet op 0 bij reset
        else
            count   <= new_count;
        end if;
    end if;
end process;

process (count)
begin
    new_count   <= count + 1;   
end process;

sensor_out  <= std_logic_vector (count);
end architecture behavioural;

this is my testbench:

 library IEEE;
 use IEEE.std_logic_1164.all;

 entity testbench is
 end entity testbench;

 architecture test of testbench is

  component sensor_control is
    port(
    clk, reset, sensor: in std_logic;
   metaal: out std_logic;
   reset_teller: out std_logic
   );
 end component;

  component counter is
   port(
   clk, reset: in std_logic;
   count_out: out std_logic_vector(10 downto 0)
   );
 end component;

 component metaal_detector is
  port(
 sensor, reset: in std_logic;
 sensor_out: out std_logic_vector(10 downto 0)
 );
 end component;

  signal sensor, clock, reset, metaal, reset_teller: std_logic; 
   signal count1, sensor1: std_logic_vector(10 downto 0);

   begin

  clock <=       '1' after  0 ns,
             '0' after 10 ns when clock /= '0' else '1' after 10 ns;
    reset   <=       '1' after 0 ns,
                     '0' after 35 ns;
    sensor   <=  '1' after  0 ns,
             '0' after 30 ns when sensor /= '0' else '1' after 30 ns;


 lblb0: sensor_control port map (clock, reset, sensor, metaal, reset_teller);                       
 lbl0: counter port map(clock, reset_teller, count1);
 lbl1: metaal_detector port map(sensor, reset_teller, sensor1);
 end architecture test;

if i use clk instead of clock somewhere is because if trying so many things.

appreciate if you could explain is i am doing something wrong.

David Kester

Upvotes: 1

Views: 1231

Answers (1)

baldyHDL
baldyHDL

Reputation: 1387

you don't need to seperate the "new_count" stuff from the "count" stuff... just combine them into one process! a counter (with a synchronous reset) is usually implemented as follows:

process (clock) 
begin
   if rising_edge(clock) then
      if reset='1' then 
         count <= (others => '0');
      else      -- or, with clock enable:  elsif clock_enable='1' then
         count <= count + 1;
      end if;
   end if;
end process;

Upvotes: 0

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