CODEWITHSUNDEEP
vhdl
Austin
Austin

Reputation: 85

VHDL When statement with multiple conditions

I am new to VHDL. I am trying to set a signals value based on the state of multiple conditions. It is outside of a process block. Is what I am trying to do even possible? If so, what am I doing wrong?

This is what I have so far:

signal1<= my_data
WHEN ( bit_cond_true
AND (my_array /= X"00000") 
AND (my_array = another_array))
ELSE
other_data;

This is what happens when I try to compile it in ModelSim:

** Error: file.VHD(62): No feasible entries for infix operator "and".
** Error: file.VHD(62): Bad expression in left operand of infix expression "and".
** Error: file.VHD(62): Type error resolving infix expression "and" as type   std.standard.boolean.
** Error: file.VHD(67): No feasible entries for infix operator "and".
** Error: file.VHD(66): Bad expression in left operand of infix expression "and".
** Error: file.VHD(67): Type error resolving infix expression "and" as type std.standard.boolean.
** Error: file.VHD(100): VHDL Compiler exiting

Upvotes: 1

Views: 27219

Answers (1)

Morten Zilmer
Morten Zilmer

Reputation: 15924

First, what you are trying to do is indeed possible, and is called a "conditional signal assignment statement" in VHDL terms.

You have not provided the declarations for the signals used in the expression, but I will assume that they are all std_logic or std_logic_vector, thus:

  signal signal1       : std_logic;                      -- Result
  signal my_data       : std_logic;                      -- Value if TRUE condition
  signal other_data    : std_logic;                      -- Value if FALSE condition
  signal bit_cond_true : std_logic;                      -- Condition part
  signal my_array      : std_logic_vector(19 downto 0);  -- --||--
  signal another_array : std_logic_vector(19 downto 0);  -- --||--

So, VHDL is a strong typed language, and the condition you have given for when can't resolve because bit_cond_true is a std_logic, and (my_array /= X"00000") resolves to a boolean. Therefore you get the ModelSim error No feasible entries for infix operator "and". since ModelSim tries to resolve an expression with {std_logic} and {boolean}, but it has no definition of the and operator with the combinations of arguments.

There are different possibilities for converting bit_cond_true to a boolean, and this goes with both VHDL-2002 and VHDL-2008:

  signal1 <= my_data when ((bit_cond_true = '1') and
                           (my_array /= X"00000") and
                           (my_array = another_array)) else
             other_data;

In VHDL-2008 only, you can also use the ?? operator to convert a std_logic value of '1' or 'H' to TRUE, and other values to FALSE. The code then looks:

  signal1 <= my_data when ((?? bit_cond_true) and
                           (my_array /= X"00000") and
                           (my_array = another_array)) else
             other_data;

To get more into the VHDL language, I would recommend that you dive into one of the books listen under "Further reading" in Wikipedia VHDL

Upvotes: 4

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