CODEWITHSUNDEEP
verilogfpgaxilinx
Mona Jalal
Mona Jalal

Reputation: 38195

Defining 1D or 2D floating point array as input port in Synthesizable Verilog

I want to define some input and output ports which are floating point so I picked up the data type real, however according to my search we cannot pass real values as input port and the available conversions are not synthesizable.

input real [0:10] delta; 
parameter ndelta= 100;
input real [0:10] ly;
input real [0:10] nly;
output real [0:20] w[0:20];
output real [0:20] oldw[0:20];

*all real values were origionally "float" values in C code.

Also I decided to make use of the floating point IP in CoreGenerator in ISE however it just does the operation on only two 32bit vectors each presenting a single floating point value. If I want to do the operation on 1D or 2D arrays of floating point number should I first customize the FP core and then use the generate for loop for creating say a 2D array? Are there some good tutorial for learning how to do a simple addition on a 1D array of floating numbers?

generate
for(i=0; (i<100); i=i+1) begin: FPU_unit
    begin
        floating_point_v5_0 U_FPU_ins(
        .a(a[i]),
        .b(b[i]),
        .clk(clk),
        .result(result[i])
        );
    end
endgenerate

Also as I am converting a C code to HDL level, I was wondering if anyone here might suggest me to use Vivado HLS for converting a portion of my C code to HDL language.

Comparing Vivado HLS and ISE which one is a more efficient method for dealing with floating point intensive calculations?

Upvotes: 2

Views: 1862

Answers (1)

EML
EML

Reputation: 10280

(1) You need to use $realtobits and $bitstoreal for passing real values across ports. Get yourself the LRM - you can find a draft version on the web; extract below.

"12.3.7 Real numbers in port connections

The real data type shall not be directly connected to a port. It shall be connected indirectly, as shown in the following example. The system functions $realtobits and $bitstoreal shall be used for passing the bit patterns across module ports. (See 17.8 for a description of these system tasks.)"

module driver (net_r);
  output net_r;
  real r;
  wire [64:1] net_r = $realtobits(r);
endmodule
module receiver (net_r);
  input net_r;
  wire [64:1] net_r;
  real r;
  initial assign r = $bitstoreal(net_r);
endmodule

(2) Use a generate. All you're doing is creating n modules, with the ports of each module connected to a different element in your array; you're over-complicating it. Try an example with an array of AND gates, for instance. You could in principle use the older 'array of instances' form, but I wouldn't do that.

(3) I wouldn't bother with tools for C conversion. You should try to understand the code and convert it yourself.

Upvotes: 2

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