Reputation: 1137
Here is my code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
--arithmetic functions with Signed or Unsigned values
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity booth is port(
m: in SIGNED(6 downto 0); -- multiplicand 2's comp
r: in SIGNED(6 downto 0); -- multiplier 2's comp
reset: in std_logic;
product: out SIGNED(13 downto 0);
clk: in std_logic
);
end booth;
architecture Behavioral of booth is
COMPONENT ALU
PORT(
X : IN SIGNED(15 downto 0);
Y : IN SIGNED(15 downto 0);
Z : OUT SIGNED(15 downto 0);
func : IN std_logic_vector(2 downto 0)
);
END COMPONENT;
SIGNAL X : SIGNED(15 downto 0) := (others=>'0');
SIGNAL Y : SIGNED(15 downto 0) := (others=>'0');
SIGNAL Z : SIGNED(15 downto 0) := (others=>'0');
SIGNAL func : std_logic_vector(2 downto 0) := (others=>'0');
type stateType is (beg, two, finish);
signal state: stateType;
SIGNAL A, S, P: SIGNED(15 downto 0) := (others=>'0');
signal count : std_logic_vector(2 downto 0) := (others=>'0');
BEGIN
foo: ALU PORT MAP(
X => X,
Y => Y,
Z => Z,
func => func
);
process(clk) is begin
if rising_edge(clk) then
if reset = '1' then
A <= (others => '0'); S <= (others => '0'); P <= (others => '0'); state <= beg;
else
case state is
when beg =>
A(15 downto 9) <= m;
A(8 downto 0) <= "0";
P(7 downto 1) <= r;
P(15 downto 8) <= "0";
P(0) <= '0';
S(15 downto 9) <= -m;
S(8 downto 0) <= "0";
state <= two;
when two =>
if P(1 downto 0) = "01" then
func <= "001"; -- P + A
X <= P;
Y <= A;
P <= Z;
elsif P(1 downto 0) = "10" then
func <= "010"; -- P - A
X <= P;
Y <= S;
P <= Z;
end if;
func <= "100"; -- ASR
X <= P;
P <= Z;
count <= count + 1;
if count = x"6" then
state <= finish;
end if;
when finish =>
product <= P(15 downto 1); --bit(s)???
end case;
end if;
end if;
end process;
end Behavioral;
I am getting the error on the two lines with P(1 downto 0) = "01"; and P(1 downto 0) = "10";
found '2' definitions of operator "=", cannot determine exact overloaded matching definition for "="
Any idea what's going on?
Upvotes: 0
Views: 5171
Reputation: 3973
Replace all of the shown context clause with the following:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
Note that NUMERIC_STD is an IEEE package and that STD_LOGIC_ARITH is shareware.
The problem you have is due to std_logic_arith having the following overloading:
function "=" (l : unsigned; r: unsigned) return boolean ;
function "=" (l : unsigned; r: signed) return boolean ;
As a result, when you try to do any comparison with a literal, it does not know whether the literal "10" is unsigned or signed. Any time you have two types that have the same literal values and you mix overloading, you have potential to have these sort of problems.
NUMERIC_STD avoids these issues by providing overloading for matching types (unsigned with unsigned) and (signed with signed) and no (unsigned with signed) or vice versa.
Another way to avoid this type of issue is by using the integer overloading. Note the sizing of the logic is determined by the array value, so be careful that the array value is large enough or otherwise the integer will be truncated on the left.
P(1 downto 0) = 1 ;
P(1 downto 0) = 2 ;
Upvotes: 3
Reputation:
Yes.
You don't appear to be using std_logic_unsigned, try commenting it's use clause out. Or better still also comment out the std_logic_signed use clause as well and introduce a use clause referencing package numeric_std.
Upvotes: 0