CODEWITHSUNDEEP
logicvhdl
user081608
user081608

Reputation: 1133

7 Segment Display with VHDL

I am currently working with vhdl and am having trouble with a 7 Segment display. I found this code online and am having trouble understand what it exactly means. Could some help me understand what is going on with the following code:

ARCHITECTURE Structure OF multi IS
 SIGNAL C : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
 LEDR <= SW;
 C(2 DOWNTO 0) <= SW(2 DOWNTO 0);

 HEX0(0) <= NOT( (NOT(C(2)) AND NOT(C(1)) AND C(0)) OR 
 (NOT(C(2)) AND C(1) AND C(0)) ); 
 HEX0(1) <= NOT( (NOT(C(2)) AND NOT(C(1)) AND NOT(C(0))) OR
 (NOT(C(2)) AND C(1) AND C(0)) ); 
 HEX0(2) <= NOT( (NOT(C(2)) AND NOT(C(1)) AND NOT(C(0))) OR 
 (NOT(C(2)) AND C(1) AND C(0)) ); 
 HEX0(3) <= NOT( (NOT(C(2)) AND NOT(C(1)) AND C(0)) OR 
 (NOT(C(2)) AND C(1) AND NOT(C(0))) OR
 (NOT(C(2)) AND C(1) AND C(0)) ); 
 HEX0(4) <= NOT( (NOT(C(2)) AND NOT(C(1)) AND NOT(C(0))) OR 
 (NOT(C(2)) AND NOT(C(1)) AND C(0)) OR 
 (NOT(C(2)) AND C(1) AND NOT(C(0))) OR (NOT(C(2)) AND C(1) AND C(0)) );
 HEX0(5) <= NOT( (NOT(C(2)) AND NOT(C(1)) AND NOT(C(0))) OR 
 (NOT(C(2)) AND NOT(C(1)) AND C(0)) OR
 (NOT(C(2)) AND C(1) AND NOT(C(0))) OR (NOT(C(2)) AND C(1) AND C(0)) ); 
 HEX0(6) <= NOT( (NOT(C(2)) AND NOT(C(1)) AND NOT(C(0))) OR
 (NOT(C(2)) AND NOT(C(1)) AND C(0)) );
END Structure;

I do not understand the logic in all the NOT and OR statements.

Thanks a lot!

Upvotes: 1

Views: 1083

Answers (1)

user1818839
user1818839

Reputation:

This is what happens when code escapes online from an Obfuscated VHDL contest.

Or perhaps being more charitable, someone junior was handed an early 1970s schematic for an octal-to-7-segment decoder chip (or circuit board!), and asked to rewrite it in VHDL because the original components are no longer available. He/she has written it out in classic "sum of products" form and not attempted to minimise it...

I believe the best thing you can do is to write out the whole thing as a lookup table, bit by bit, and not worry about the details of the logic.

Start with each expression...

 HEX0(6) <= NOT( (NOT(C(2)) AND NOT(C(1)) AND NOT(C(0))) OR
 (NOT(C(2)) AND NOT(C(1)) AND C(0)) );

And minimise it

 HEX0(6) <= NOT((NOT(C(2)) AND NOT(C(1)));

And write it out for each value

C  C2  C1  C0  H6  H5  H4  H3  H2  H1  H0   HEX0
0   0   0   0   0   0   0   1   0   0   1   0001001 = 09
1   0   0   1   0
2   0   1   0   1
3   0   1   1   1
4   1   0   0   1
5   1   0   1   1
6   1   1   0   1
7   1   1   1   1

(Not complete and not guaranteed correct either...)

Then rewrite the thing along these lines:

subtype Seven_Seg is std_logic_vector(6 downto 0);

constant Lookup : array(0 to 7) of Seven_Seg := ( 0 => "0001001",
                                                  1 => ...
                                                  ...
                                                  7 => ... );

Hex0 <= Lookup(to_integer(unsigned(C)));

and be done with it.

Upvotes: 5

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