CODEWITHSUNDEEP
vhdlclockfpgaxilinx
Ant
Ant

Reputation: 281

Use DCM for generate clock of 78 mhz from 100 mhz clock

I have a clock of 100 mhz. I want to use DCM to create a clock of 78 mhz.

I think I should use two DCM, where the output of first DCM goes into the second DCM but I don't know if this will work.

Best Regards

Upvotes: 0

Views: 1161

Answers (3)

Kevin Thibedeau
Kevin Thibedeau

Reputation: 3421

Rather than using a DCM directly you can investigate using a Direct Digital Frequency Synthesizer (DDFS). It amounts to an accumulator that is incremented by a constant count value. You can control the precision by the size of the accumulator.

It is helpful if there is as much disparity between the accumulator clock and the generated frequency as possible. Consider using a DCM to scale the 100MHz up to the highest speed you can run a counter of the necessary width and still meet timing for your target device. There will be some jitter equal to one period of whatever clock is driving the accumulator but the average frequency can be made very close to 78 MHz.

accum_freq = 100 MHz * DCM_MULTIPLIER
accum_size = ceil(log2(accum_freq / (78 MHz * tolerance)))
increment = 78 MHz / accum_freq * 2**accum_size

accum = accum + increment

You then tap off the MSB of the accumulator to get your synthesized 78 MHz clock.

You can either manually compute these constants for use as magic numbers or do the arithmetic natively in VHDL to define the size and increment as machine computed constants. By reducing the tolerance you will increase the required size of the accumulator. Start off with 0.01% (0.0001) and see if it is satisfactory.

Upvotes: 3

Martin Thompson
Martin Thompson

Reputation: 16822

What device are you targeting? On a Spartan-6 the DCM_CLKGEN allows a multiplier of 39 and a divider of 50, which gets you your 78MHz.

Upvotes: 1

Russell
Russell

Reputation: 3465

If you set your multiplier to 7 and your divider to 9 you'll be able to get to 77.77 MHz. Will that work for you?

Upvotes: 1

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