CODEWITHSUNDEEP
verilogfpgasystem-veriloghdl
jandrew
jandrew

Reputation: 21

Syntax errors in the verilog code

I want to convert this c code to verilog module but I am having some difficulty

void window_averaging(void) {

  register unsigned int i, k;
  for (i = 0; i < 128; i++) {
    // Copying first 128 output samples to the Window 0 and so on till Window 7.
    W[count][i] = O[i];
  }


  for (i = 0; i < 128; i++) {
    for (k = 0; k< 8; k++) {
      O[i] += W[k][i];
    }
    O[i] /= 8; // Averaging over 8 window
  } 
  count = (count++)%8; // Count = 0  after all the window elements are filled.
}

Verilog:

module window_averaging(
  input      [16:0]in_noise, //input from noise cancellation
  input            clk,
  output reg [16:0]window_average // output after window averaging
  );

integer i;
integer k;
integer count = 0;
reg [16:0] store_elements[0:7][0:128]; //  2-D array for window averaging
reg [16:0] temp;

always @(posedge clk)
begin
  //  Copying first 128 output samples to the Window 0 and so on till Window 7
  for(i=0 ; i < 128 ; i = 1+1)
  begin
    store_elements[count][i] = in_noise;
  end
  for(i=0; i<128 ; i=i+1)
  begin
    for(k=0;k<8;k = k+1)
    begin
      temp = temp + store_elements[i][k];
    end
    window_average = temp/8;
    count = (count+1)%8;
  end
end
endmodule

The errors I am getting are syntax error near "(" and "=". I am little new to verilog can anyone help me how to proceed.

Upvotes: 2

Views: 1172

Answers (2)

Noobification
Noobification

Reputation: 319

I don't know what you are using to compile, but I think the following stuff should give you errors:
For the first loop: 

for(i=0 ; i < 128 ; i = 1+1)

change to i= i+1


Also, in line:

temp = temp + store_elements[i][k];

remember the declaration store_elements[0:7][0:128] , so may be switch i and k ?




This isn't an answer really. Sorry, I don't have comment privilege yet.

Upvotes: 1

Tommy
Tommy

Reputation: 622

First you are trying to drive a wire from inside an @always block which is not allowed. If you convert the wires to regs then it will work:

    module window_averaging(
    input [16:0]in_noise, //input from noise cancellation
    input clk,
    output reg [16:0]window_average // output after window averaging
    );

    integer i;
    integer k;
    integer count = 0;
    reg [16:0] store_elements[0:7][0:128]; //  2-D array for window averaging
    reg [16:0] temp;
    ...

Also I believe to be consistent with your C code the line count = (count+1)%8; should be outside the for loop like so:

    window_average = temp/8;
    end
    count = (count+1)%8;
    end
    endmodule

Upvotes: 1

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