Reputation: 2935
Here is my stripped example:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity queue is
port(
reset: in std_logic;
input_ready: out std_logic
);
end entity;
architecture reference of queue is
signal queue_size: unsigned(15 downto 0);
begin
process
begin
input_ready <= (reset = '0') and (queue_size < 1024);
end process;
end architecture;
Where this line:
input_ready <= (reset = '0') and (queue_size < 1024);
produces
no function declarations for operator "and"
ghdl: compilation error
when running
ghdl -a queue.vhdl
with GHDL 0.32rc1 (20141104) [Dunoon edition]
on Arch Linux.
According to VHDL operators both comparisons return boolean and there is and
definition for two booleans. So what am I doing wrong?
Upvotes: 0
Views: 3148
Reputation: 16221
The two sub expressions (reset = '0')
and (queue_size < 1024)
return a boolean value. The and
operator also returns a boolean result, which you are trying to assign to a std_logic output.
The solution:
input_ready <= '1' when (reset = '0') and (queue_size < 1024) else '0';
Note: This line needs no surrounding process.
Upvotes: 4