VHDL Synthesize Block Ram with Multiple Outputs

Question

if rising_edge(CLK_100Mhz) then
  if w_ram = '1' then
    for X in 0 to 6 loop
        for Y in 0 to 6 loop
            DataO(X)(Y)(0) <= Memory(X)(Y)(Address);
            DataO(X)(Y)(1) <= Memory(X)(Y)(Address+1);
            DataO(X)(Y)(2) <= Memory(X)(Y)(Address+2);
            DataO(X)(Y)(3) <= Memory(X)(Y)(Address+3);
            Memory(X)(Y)(Address) <= DataI(X)(Y)(0);
        end loop;
    end loop;
  w_ram <= '0';
end if;
end if;

I need to use block ram for my data intensive project. Would this work as a 1 input, 4 output block for every given X,Y or would this create 4 blocks for every given X,Y? Also would this even work? I'm using a Xilinx Zynq-7000 FPGA.

Thanks.

Answer 1

I'm guessing you want the Xilinx synthesis tool to infer multiple asymmetric block RAMs. Xilinx has sample code to infer one RAM, which can be found at

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_2/xst_v6s6.pdf

The write port is 8 bits wide and 256 deep and the read port is 32 bits wide and 64 deep. Here's the code from the above link:

-- Asymmetric port RAM
-- Port A is 256x8-bit write-only
-- Port B is 64x32-bit read-only
--
-- Download: ftp://ftp.xilinx.com/pub/documentation/misc/xstug_examples.zip
-- File: HDL_Coding_Techniques/rams/asymmetric_ram_1a.vhd
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity asymmetric_ram_1a is
generic (
    WIDTHA      : integer := 8;
    SIZEA       : integer := 256;
    ADDRWIDTHA  : integer := 8;
    WIDTHB      : integer := 32;
    SIZEB       : integer := 64;
    ADDRWIDTHB  : integer := 6
);
port (
    clkA    : in    std_logic;
    clkB    : in    std_logic;
    weA     : in    std_logic;
    enA     : in    std_logic;
    enB     : in    std_logic;
    addrA   : in    std_logic_vector(ADDRWIDTHA-1 downto 0);
    addrB   : in    std_logic_vector(ADDRWIDTHB-1 downto 0);
    diA     : in    std_logic_vector(WIDTHA-1 downto 0);
    doB     :   out std_logic_vector(WIDTHB-1 downto 0)
);
end asymmetric_ram_1a;

architecture behavioral of asymmetric_ram_1a is

function max(L, R: INTEGER) return INTEGER is
begin
    if L > R then
        return L;
    else
        return R;
    end if;
end;

function min(L, R: INTEGER) return INTEGER is
begin
    if L < R then
        return L;
    else
        return R;
    end if;
end;

constant minWIDTH : integer := min(WIDTHA,WIDTHB);
constant maxWIDTH : integer := max(WIDTHA,WIDTHB);
constant maxSIZE  : integer := max(SIZEA,SIZEB);
constant RATIO    : integer := maxWIDTH / minWIDTH;

type ramType is array (0 to maxSIZE-1) of std_logic_vector(minWIDTH-1 downto 0);
signal ram : ramType := (others => (others => '0'));
signal readB : std_logic_vector(WIDTHB-1 downto 0):= (others => '0');
signal regB : std_logic_vector(WIDTHB-1 downto 0):= (others => '0');

begin
process (clkA)
begin
    if rising_edge(clkA) then
        if enA = '1' then
            if weA = '1' then
                ram(conv_integer(addrA)) <= diA;
            end if;
        end if;
    end if;
end process;

process (clkB)
begin
    if rising_edge(clkB) then
        if enB = '1' then
            readB(minWIDTH-1 downto 0)
            <= ram(conv_integer(addrB&conv_std_logic_vector(0,2)));
            readB(2*minWIDTH-1 downto minWIDTH)
            <= ram(conv_integer(addrB&conv_std_logic_vector(1,2)));
            readB(3*minWIDTH-1 downto 2*minWIDTH)
            <= ram(conv_integer(addrB&conv_std_logic_vector(2,2)));
            readB(4*minWIDTH-1 downto 3*minWIDTH)
            <= ram(conv_integer(addrB&conv_std_logic_vector(3,2)));
        end if;
    regB <= readB;
    end if;
end process;

doB <= regB;

end behavioral;

Here's an excerpt the synthesis report confirming that XST infers an asymmetric memory.

Synthesizing (advanced) Unit <asymmetric_ram_1a>.
INFO:Xst:3226 - The RAM <Mram_ram> will be implemented as a BLOCK RAM, absorbing the following register(s): <readB> <regB>
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 256-word x 8-bit                    |          |
    |     mode           | write-first                         |          |
    |     clkA           | connected to signal <clkA>          | rise     |
    |     weA            | connected to signal <weA_0>         | high     |
    |     addrA          | connected to signal <addrA>         |          |
    |     diA            | connected to signal <diA>           |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 64-word x 32-bit                    |          |
    |     mode           | write-first                         |          |
    |     clkB           | connected to signal <clkB>          | rise     |
    |     enB            | connected to signal <enB>           | high     |
    |     addrB          | connected to signal <addrB>         |          |
    |     doB            | connected to signal <doB>           |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
Unit <asymmetric_ram_1a> synthesized (advanced).

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 1
 256x8:64x32-bit dual-port block RAM                   : 1

Note, port B is read-only despite what the synthesis report says.