CODEWITHSUNDEEP
scalahardwareveriloghdlchisel
Joan
Joan

Reputation: 4320

Dependency on Verilog libs

Is it possible to depend on some already coded Verilog libs in Scala Chisel?

If not that looks to me like a feature as major as Scala's Java retro-compatibility, which made the success of Scala in the soft world.

Cheers

Upvotes: 1

Views: 178

Answers (1)

dk14
dk14

Reputation: 22374

You may include some external module as a blackbox:

12 BlackBox

Black boxes allow users to define interfaces to circuits defined outside of Chisel. The user defines:

a module as a subclass of BlackBox and an io field with the interface. For example, one could define a simple ROM blackbox as:

class RomIo extends Bundle { 
  val isVal = Bool(INPUT) 
  val raddr = UInt(INPUT,  32) 
  val rdata = UInt(OUTPUT, 32) 
} 
 
class Rom extends BlackBox { 
  val io = new RomIo() 
}

Unfortunatelly, I didn't find any tool to generate blackboxes from .v files. It seems that you have to define all required types/interfaces by yourself (using Bundle). About importing - all .v files in the same folder are automatically available (so you can just put your library.v right next to generated .v files), but sometimes you may need to manually add some more complex includes into generated .v files. So it's not much handy yet.

Upvotes: 3

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