CODEWITHSUNDEEP
vhdlsequentialdataflowshift-register
ali amani
ali amani

Reputation: 35

Illegal sequential statement error

please can anyone tell me how to fix this code?

what is the Illegal_sequential_statement error(in modelSim)?

why it say that near when nead ';' (in quartus) ?

LIBRARY ieee ;
USE ieee.std_logic_1164.all;

ENTITY Shift_reg IS
PORT( Par_LD: IN std_logic_vector(7 DOWNTO 0);
      Serial_In: IN std_logic;
      Serial_Out:OUT std_logic;
      RST, LD, EN, CLK: IN std_logic);
END Shift_reg;


ARCHITECTURE shiftRegARCH OF Shift_reg IS 

SIGNAL TEMP_REG : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL TEMP_SOUT : STD_LOGIC;

BEGIN

process(CLK,RST)
  BEGIN 

    TEMP_REG <= (OTHERS => '0') WHEN (RST = '1') ELSE 
                 Par_LD WHEN (EN = '0' AND LD = '1')ELSE
                (Serial_In & TEMP_REG(7 DOWNTO 1)) WHEN (EN = '1')ELSE
                TEMP_REG ;                
    TEMP_SOUT <= TEMP_REG(0) WHEN (EN = '1') ELSE TEMP_SOUT;
    Serial_Out <= TEMP_SOUT;
  END PROCESS;


END shiftRegARCH ;

Upvotes: 3

Views: 1582

Answers (2)

user1155120
user1155120

Reputation:

In addition to lasplund noting that a sequential conditional signal assignment is only supported in VHDL -2008 compliant tools which can sometimes be cured with tool configuration or command line arguments, you are not using a recognized construct to indication sequential (clocked) hardware.

Synthesis doesn't interpret the presence of CLK in the sensitivity list as inferring clocked storage, and there will like be both rising edge and falling edge events on CLK.

This pretty much says you should use an equivalent if statement with a recognized form to infer clocked hardware:

library ieee;
use ieee.std_logic_1164.all;

entity shift_reg is
    port ( 
        par_ld:     in  std_logic_vector(7 downto 0);
        serial_in:  in  std_logic;
        serial_out: out std_logic;
        rst, ld, 
        en, clk:    in  std_logic
    );
end entity shift_reg;


architecture shiftregarch of shift_reg is 
    signal temp_reg:    std_logic_vector(7 downto 0);
    -- signal temp_sout:   std_logic;
begin

    process(clk,rst)
    begin 
        -- temp_reg <= (others => '0') when (rst = '1') else
        --              par_ld         when (en = '0' and ld = '1') else
        --             serial_in & temp_reg(7 downto 1)
        --                             when (en = '1');
        --    --         temp_reg ;   
        if  rst = '1' then
            temp_reg <= (others => '0');
            serial_out <= '0';
        elsif rising_edge(clk) then
            if en = '0' and ld = '1' then
                temp_reg <= par_ld;
            elsif en = '1' then
                temp_reg <= serial_in & temp_reg( 7 downto 1);
                serial_out <= temp_reg(0);
            end if;
        end if;

        -- temp_sout <= temp_reg(0) when (en = '1') else temp_sout;
        -- serial_out <= temp_sout;
    end process;
end architecture shiftregarch;

Note the lack of final elses which are redundant in sequential storage, as well as throwing out temp_sout as not needed and resetting serial_out and including it in the en umbrella.

There's a section in one of the Quartus II manuals entitled Recommended HDL Coding Styles displaying Altera's recommendation for expressing clocked logic. It's not all inclusive as the now withdrawn IEEE Std 1076.6-2004 gives several other forms.

It contains several shift register examples and discusses default values and secondary controls.

The method shown with the rising_edge function is found in 1076.6.

While Lars addressed your immediate error it's likely you would have encountered additional errors.

Upvotes: 3

lasplund
lasplund

Reputation: 1440

The conditional signal assignment

    TEMP_REG <= (OTHERS => '0') WHEN (RST = '1') ELSE
             Par_LD WHEN (EN = '0' AND LD = '1')ELSE
            (Serial_In & TEMP_REG(7 DOWNTO 1)) WHEN (EN = '1')ELSE
            TEMP_REG ;

is only valid with VHDL 2008. You probably have your compiler settings set to VHDL 2002 or VHDL 93

Upvotes: 4

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