CODEWITHSUNDEEP
indexingverilogcounterxilinxsynthesis
user2921643
user2921643

Reputation: 85

Indexed part select synthesizable in verilog

Can I use something like code below (counter value in vector index) in my verilog code?

data_out[cnt*32 + 31 : cnt*32] = data_in;

Is this construct synthesizable in xst? I've got a constant defined data_out range and cnt is incremented on clock and never reaches value greater than max range of data_out. Everything else is synchronous to one clk.

Upvotes: 2

Views: 3078

Answers (3)

Adapa
Adapa

Reputation: 1

I think in the above statement: data_out[cnt*32 + 31 : cnt*32] = data_in; if cnt = 0, it will be data_out[31:0] = data_in;.

Also, same statement can be written as data_out[cnt*32 +: 32] = data_in; as explained by Morgan.

Upvotes: 0

Morgan
Morgan

Reputation: 20514

I am pretty sure your example will not compile however from Verilog 2001 you can do this:

data_out[cnt*32 +: 32] = data_in;

Section 5.2.1 in IEEE 1364-2005 Vector bit-select and part-select addressing

Or Section 7.4.3 of IEEE 1800-2012.

Upvotes: 2

Krouitch
Krouitch

Reputation: 626

I am quite confident in saying that you cannot synthesize this with any synthesizer.

As I understand it you want to keep the previous values(of lower indexes) of the output when your counter increments. I do not see how to do it without registers.

In my opinion, a way to do it would be to store each 32bits in registers(enabled by the counter value) and assign to the output the concatenation of these registers.

Upvotes: 1

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