CODEWITHSUNDEEP
simulationverilogfpga
Frank Dejay
Frank Dejay

Reputation: 739

Xilinx, Isim treatment of Verilog integer types in simulation

I'm pretty new to FPGA and Verilog, but I'm having a problem getting my code to run in the simulator they way I would expect. It seems the Isim simulator is not "operating" on integers in my code. Below is a snippet of the relevant code. I'm trying to divide the clk pulse by toggling SCK_gen every time integer i reaches 10. When I run this code in Isim, SCK_gen never changes value. Also it When I impliment the code on the FPGA, it behaves as I would expect, I can observe a pulse at 1/10 the clock frequency. If anyone can point me in the right direction I'd be grateful. Thanks

    //signals
//for SCK_clock
reg SCK_gen, SCK_hold;
integer i;
reg en_SCK;
wire neg_edge_SCK;


//SCK_generator
always @(posedge clk, posedge reset)
    if (reset)
        begin 
            SCK_gen <= 0;
        end
    else
        begin
            i <= i+1;
            SCK_hold <= SCK_gen;
                if(i == 10)
                    begin
                        SCK_gen <= ~SCK_gen;
                        i <= 0;
                    end
        end

//detect neg edge of SCK
assign neg_edge_SCK = SCK_hold & SCK_gen;

Upvotes: 2

Views: 671

Answers (1)

user597225
user597225

Reputation:

The result of any arithmetic or logical equality operation is 'x' if any of the operands are 'x'. Since it looks like i is not initialized, the statement i <= i+1 has no effect on i and so the comparison (i == 10) will always be false.

Upvotes: 4

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