CODEWITHSUNDEEP
system-veriloguvm
noobuntu
noobuntu

Reputation: 913

Does SystemVerilog support nested packages?

I have a tool that produces .sv RAL files for use in a UVM testbench. The problem is that this file creates the register block as a package. My issue is that for my testbench, I want to import multiple .sv RAL files (representing different reg blocks).

To do this, I want to create a single package all_my_regs_pkg.sv and `include the other packages into this package. I get a compilation error and looking into it, it looks like there isn't support for nested packages in SystemVerilog.

So do I need to manually import each of the reg block packages when I want to use them? I suppose I could create a file with the imports and just `include it, but is this the only way?

Upvotes: 1

Views: 5187

Answers (1)

dave_59
dave_59

Reputation: 42748

SystemVerilog does not allow nesting of package declarations. The best thing for you do do is to define a file that is a list of package import statements and have users `include that file where needed.

The is another SV feature that allows you to chain package imports, but you have to explicitly export a symbol that you import into a package to be imported by the next package. See Section 26.6 Exporting imported names from packages in the 1800-2012 LRM

Upvotes: 5

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