Reputation: 33
I am new to verilog, can anyone please explain me how does these statements execute.
always@(posedge clock) begin
A <= B ^ C;
D <= E & F;
G <= H | J;
K <= G ? ~&{A,D} : ^{A,D}
end
As far I can tell, the right side is first executed. Hence, the values for A, D, G, K are first calculated. While calculating value for K, depending on value of G the either first or second expression would execute. Can anyone please explain this operation. Please also tell how the last statement gets synthesized as this entire code is inside a always block and with positive edge clock. Thanks in advance.
Upvotes: 1
Views: 492
Reputation: 4381
A nonblocking assignment evaluates the RHS expression at the beginning of a time step and schedules the LHS update to take place at the end of the time step.
In Verilog, there is a well defined event queue as shown below. For each and every timestamp, all the regions are evaluated. If there are any events to be executed in current timestamp, then they are triggered. Once all the events of current timestamp are triggered, then only simulation time moves forward.
Here, the RHS of ALL the expressions are evaluated at the beginning of the timestamp of posedge of clock. Hence, the values of B^C
, E&F
,H|J
,G ? ~&{A,D} : ^{A,D}
are evaluated and stored internally in the simulator.
Thereafter, the LHS are updated as the simulation progresses to NBA region of the same timestamp.
The values of G,
Aand
Dare not updated in active region. Hence, while calculating the value of
K, the previous values of
G,
Aand
Dare taken in the Active region. Then, all the veriables;
G,
A,
Dand
K` are updated simulatanously.
I have made an example code over EDAPlayground. The waveforms might be helpful.
As far as last statement is concerned, I guess it will create a flop with mux (with Select=G
and Inputs as nand(A,D)
, xor(A,D)
) as input.
Upvotes: 1