CODEWITHSUNDEEP
system-verilog
imulsion
imulsion

Reputation: 9040

Why does this statement introduce memory?

I'm learning SystemVerilog and today my lecturer warned us against accidentally introducing memory into combinational systems. He used the following code as an example of this:

module gate(output logic y, input logic a);
       always_comb
          if(a)
             y = '1;
endmodule

However, I don't understand why this presents a problem. As far as I can see, this is just a simple buffer. In what way does this code introduce memory into the system?

Upvotes: 1

Views: 122

Answers (1)

Matthew
Matthew

Reputation: 13967

At the beginning of the simulation if a == 0 the value of y will be '0. If later a == 1'b1 then y will become '1. What value do you expect y to have when later on a == 0?

The answer to this question is that it will retain its previous value: '1. That is not the behaviour of combinational logic, whose output by definition only depends on the current state of the inputs, not on their previous states. In order to implement the behaviour you have described, the synthesiser will need a component with state, with storage, with memory. It will fulfill this by using a latch.

Upvotes: 4

Related Questions