CODEWITHSUNDEEP
vhdl
HAREESH
HAREESH

Reputation: 13

Component instantiation error

For the following VHDL code:

library ieee;
use ieee.std_logic_1164.all;
entity dff is
  port(
      d, clk: in std_logic;
      q: out std_logic);
end dff;
architecture behave of dff is
  begin
    process(clk)
      begin
      if(clk = '1') then
        q<= d;
    end if;
  end process;
end behave;

---------------------------------------------------------------------

and and a testbench:

library ieee;
use ieee.std_logic_1164.all;
entity dff is
end dff;
architecture behave of dff is
  component dff is
port(d, clk: in std_logic;
     q: out std_logic);


 end component;


    signal  d_in: std_logic;
    signal  clk_in: std_logic;
    signal  q_out: std_logic;

begin
  d_ff : dff port map( d_in, clk_in, q_out);
  process
    begin
      if(clk_in = '1') then
      q_out<= d_in;
      end if;
  end process;
end behave;

When trying to simulate Modelsim is showing the following error:

#Error loading design
The following component ports are not on the entity:
     q
     clk
     d

Upvotes: 2

Views: 1503

Answers (1)

Matthew
Matthew

Reputation: 13937

The entity name of your testbench is also dff. You need to give it a different name (eg dff_tb). So, when you compile your testbench, it is overwriting the other dff entity.

Upvotes: 4

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