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image-processingvhdlfpgaxilinxvivado
ikramulhaq
ikramulhaq

Reputation: 43

Read and Write Image Block into DDR using Vivado IP Block

We are working on project where we need to do some image processing on FPGA. For that purpose we are using ZedBoard with linaro (Ubuntu Version) running on it. What we have already done is we have stored the image in binary form pixel by pixel in DDR using python script on Processing System of Zedboard.

Now our task is to read the content of DDR memory, process it and send back the processed output to DDR Memory again. We are using vivado xilinx tool for FPGA part. We tried to use AXI-DMA with AXI-Interconnect to read and write data from DDR. My question is, Do We need to use SDK and some sort of C coding to read and write DDR Memory on Programmable Logic side? As we want to make our module start reading the data from DDR with a control signal and then start actual processing of Image data. Once we read specific block of data, process it and store the result back to DDR memory on the fly. We are not sure which IP Block do we need in our block design for vivado. Also do we need Block Ram Memory at the end before sending the date to DDR.

Can anyone who already done this sort of project or have any knowledge ? Any help from your side will be appreciated !

Thanks

Upvotes: 0

Views: 1866

Answers (1)

Nathanael
Nathanael

Reputation: 77

The zynq FPGA provide an AMBA AXI interconnect for that purpose.

Zynq FPGA overview

This is the interconnect on the right.

Upvotes: 0

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