CODEWITHSUNDEEP
moduleverilog
fhw72
fhw72

Reputation: 1156

Recommended order of input and output ports in Verilog module declaration

Being new to Verilog I noticed that lots of code is ordering their ports in module declarations with inputs first:

module do_something(
    input wire clk_in,
    input wire a_in,
    input wire b_in,
    output reg val_out);
....
endmodule

(Almost the same way I'm used to it when programming in C/C++: inputs first, then outputs).

However I've also seen examples with an opposite order of parameters (output first, inputs last).

I hope this isn't a too dumb question:

Is there any recommendation/best practice to prefer one over the other? So far I'd simply stick to "inputs first" but I wanted to ask before forming a bad habit.

Upvotes: 1

Views: 3560

Answers (3)

Charles Clayton
Charles Clayton

Reputation: 17946

As others have said, it's convention to put clocks and resets first, then other generic inputs, then outputs.

However, as a personal convenience, I like to put the clocks and resets at the bottom, because these are signals that you are unlikely to modify. This means you don't have to deal with trailing commas or missing commas as you refactor your code by adding/removing ports. For instance:

module example_module(input  wire       clk,
                      input  wire [7:0] a, 
                      input  wire       b,       
                      output wire [7:0] x,            
                      output wire       y 
);

If you needed to add another output port after output wire y, you would have to make sure you added a comma after the y. Similarly, if you removed the output wire y, you would have to make sure you deleted the comma after the x.

This is a small thing but is an accumulated inconvenience when you're hooking things up and rearranging signals and moving ports around. Whereas if you used the following, you could add or remove ports and never have to mess with the trailing commas.

module example_module(input  wire [7:0] a, 
                      input  wire       b,       
                      output wire [7:0] x,            
                      output wire       y,

                      input  wire       clk    
);

And it's the same thing for when you instantiate the module.

example_module u__example_module (
     .a  (a),
     .b  (b),
     .x  (x),
     .y  (y),
     .clk(clk)
);

It's a subjective answer, but hey, it's a subjective question.

Upvotes: 1

dave_59
dave_59

Reputation: 42658

Verilog built-in primitives have their output first followed by their inputs. When connecting module ports, you should be connecting by port names, not positional order, so the order does not really matter.

Upvotes: 1

Brian Magnuson
Brian Magnuson

Reputation: 1487

Usually I do clocks and resets first. Followed by IO grouped by function if it's a large module that has more than one 'thing' going on at once. Within a group I usually order inputs first and then outputs, but the other way is also fine.

Ultimately it's a matter of style so the most important thing is to be consistent. Pick a style and stick with it.

Upvotes: 2

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