CODEWITHSUNDEEP
verilogsystem-verilog
qwertyuiop
qwertyuiop

Reputation: 47

Can I reduce the number of bits after Arithmetic Right Shift?

If I reduce the number of bits after arithmetic right shift in verilog, do I still get the correct signed number? Is this valid?

number of bits reduced = shift value

A = 1110_1110
A>>>1
new A = 111_0111

Upvotes: 0

Views: 576

Answers (1)

Oldfart
Oldfart

Reputation: 6259

Yes, but you should use three '>' not four and of course the new variable should be big enough:

wire signed [7:0] A,B;
wire signed [6:0] just_fits;
wire signed [5:0] oops;

  assign         B = A >>> 1;  // Signed divide by two
  assign just_fits = A >>> 1;  // Signed divide by two
  assign      oops = A >>> 1;  // Goes wrong

Upvotes: 1

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