Reputation: 3657
I have the following wires in verilog:
wire [15:0] mywire;
wire [7:0] mywire_shifted
wire [4:0] shiftamount;
I want to shift mywire left by some amount, but only retain the upper 8 bits:
assign mywire_shifted = (mywire << shiftamount) >> 8;
Is there a cleaner way to do this?
Perhaps something like this:
assign {mywire_shifted,8'0} = mywire << shiftamount;
Upvotes: 0
Views: 1493
Reputation: 42613
I think your first solution is clean. But you could also do
assign mywire_shifted = mywire[shiftamount+8 +: 8];
This says starting from the LSB (shiftamount+8) return the next MSB(higher) 8 bits.
Upvotes: 5