CODEWITHSUNDEEP
verilog
Robyn Pan
Robyn Pan

Reputation: 63

How to connect inout signal to output and input port

PS_GPIO is a 56 bits "inout" signal in module "xillydemo". Now I want to assign different part of PS_GPIO to three different port in top module:

module xilly_mydemo(
  input  clk_100,
  input  otg_oc,   
  inout [23:0] PS_GPIO1,
  output [23:0] PS_GPIO2,
  input [7:0] PS_GPIO3,
  output [3:0] GPIO_LED,
  output [3:0] vga4_blue,
  output [3:0] vga4_green,
  output [3:0] vga4_red,
  output  vga_hsync,
  output  vga_vsync,

  output  audio_mclk,
  output  audio_dac,
  input   audio_adc,
  input   audio_bclk,
  input   audio_lrclk,    
  output smb_sclk,
  inout  smb_sdata,
  output [1:0] smbus_addr,      
  output [23:0] sig_out); 

  wire [23:0]PS_GPIO1;
  wire [23:0]PS_GPIO2;
  wire [7:0] PS_GPIO3;

 xillydemo xillydemo(
    .clk_100(clk_100),
    .otg_oc(otg_oc),   
    .PS_GPIO(PS_GPIO),
    .GPIO_LED(GPIO_LED),
    .vga4_blue(vga4_blue),
    .vga4_green(vga4_green),
    .vga4_red(vga4_red),
    .vga_hsync(vga_hsync),
    .vga_vsync(vga_vsync),

    .audio_mclk(audio_mclk),
    .audio_dac(audio_dac),
    .audio_adc(audio_adc),
    .audio_bclk(audio_bclk),
    .audio_lrclk(audio_lrclk),    
    .smb_sclk(smb_sclk),
    .smb_sdata(smb_sdata),
    .smbus_addr(smbus_addr),      
    .sig_out(sig_out)
  ); 

  assign PS_GPIO1 = PS_GPIO[23:0];
  assign PS_GPIO2= PS_GPIO[24:47];  
  assign PS_GPIO3=PS_GPIO[48:55];
  endmodule

But it shows "cannot index into non-array type wire for PS_GPIO". Can anyone help me out? Thanks!

Upvotes: 2

Views: 1246

Answers (1)

Oldfart
Oldfart

Reputation: 6259

You have not defined PS_GPIO anywhere so Verilog assumes a single bit.

Even if that is fixed, I don't think you are on the right track. Messing about with inout and splitting it in input, output and inout ports is at least confusing. I am not even sure the tool will accept it as written there.
Make a clean design, make three ports in xillydemo one input, one output and one inout all of the correct width.

Upvotes: 0

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