CODEWITHSUNDEEP
verilogsystem-verilog
Nandhini
Nandhini

Reputation: 61

Is it possible to do indexed instantiation?

I have a file that is something similar to:

module AB(A,B,Out);
  input A,B;
  output Out;

  wire Out;
  assign Out = A & B;
endmodule

I need to use N number of this calculation. For example, I have a=1001; b=0001, and I need to do something like bitwise AND, and I have N bits.

I have used it as an instantiation:

op[0] = a[0] & b[0];
op[1] = a[1] & b[1];
op[2] = a[2] & b[2];
op[3] = a[3] & b[3];
op[4] = a[4] & b[4];

When I'm trying to do this with an index i, I have:

AB g(a[i],b[i],Op[i]) for i = 0 to N-1.

If I do this, it says AB is undeclared.

Is this possible? If so, what is the alternative?

Upvotes: 6

Views: 12612

Answers (2)

Marty
Marty

Reputation: 6654

You've a few options:

  • Parameterise bus sizes in your module
  • Array of instances
  • generate statements

But to answer the question, it is possible to do arrays of instances. Here's what the syntax looks like for your AB module.

module testbench ();
   localparam WIDTH = 4;

   reg [WIDTH-1:0] a_in, b_in;
   wire [WIDTH-1:0] out_a;

   AB u0[WIDTH-1:0]
     (
      .A(a_in),
      .B(b_in),
      .Out(out_a)
     );

   initial begin
      ...
   end

endmodule

Here, a_in[3], b_in[3] and out_a[3] are mapped to the ports of u0[3].

Upvotes: 9

toolic
toolic

Reputation: 62096

This is possible using the generate statement which supports an array of instances. This construct was introduced in the Verilog IEEE Std 1364-2001.

genvar i;
generate
    for (i=0; i<4; i=i+1) begin
        AB g (a[i], b[i], op[i]);
    end
endgenerate

Upvotes: 6

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