CODEWITHSUNDEEP
verilogsystem-verilog
Shreyas Kv
Shreyas Kv

Reputation: 13

What is the maximum wire bit-width in verilog/system verilog

I am trying to synthesize a design using Intel Quartus software. During synthesis flow, I got a warning stating "Verilog declaration warning: vector has more than 2**16 bits". Due to project specifications, the wire length exceeds 2^16 bits. Do I really need to worry about this warning? Is there any constraint in Verilog/System Verilog regarding maximum bit-width of the wires?

Upvotes: 1

Views: 5486

Answers (3)

dave_59
dave_59

Reputation: 42623

Yes, you should worry about the messages. It means you are probably miscoding something as I do not believe you really need an integral vector (packed array) with 2^16 bits. This means want to represent a number as great as 2^16^2 = 1.1579209e+77. You probably want an unpacked array of bits or bytes.

Upvotes: 0

Silicon1602
Silicon1602

Reputation: 1181

Yes, according to the the SystemVerilog LRM it can be limited, and since your synthesis tool is throwing a warning, you should keep this in mind if any issues arise in the future of your project.

For packed arrays (Section 7.4.1), which you are probably referring to according to the warning, the aformentioned LRM reads:

The maximum size of a packed array can be limited, but shall be at least 65 536 (2^16) bits.

For unpacked arrays (Section 7.4.2), it says:

Implementations may limit the maximum size of an array, but they shall allow at least 16 777 216 (2^24) elements.

But, do you actually need a 2^16 bit wide vector? If you have a 16 bit variable (e.g., logic [15:0]), you can handle unsigned values up to 2^16-1 = 65535. If you have a 2^16 bit wide vector (e.g., logic [65535:0]), you could display values up to 2^(2^16)-1 ≈ 2.00 × 10^19728.

Could you not split up your wire into a couple of smaller wires?

Upvotes: 0

Greg
Greg

Reputation: 19094

The Verilog/SystemVerilog languages themselves do not define a maximum vector width. I vaguely remember a minimum for simulations mention somewhere in the IEEE1364 / IEEE1800 LRMs.

Synthesizers can have their own limitations for various reasons; ex software complexity, physical mapping/routing, business tactics (“buy this other tool”), etc. The fact you are getting warnings probably suggests physical mapping/routing as most synthesizers try to keep all the bits in a vector together; thereby making overall routing and clock-tree buffering easier.

2^16 is a lot of bits and your design exceeds that. In theory you could split the whole vector into more manageable chunks (ex left, right) and it might give you better routing and timing. If your design is meeting all requirements, then the warning could be ignored. Just be ready to make changes when it suddenly can no longer be ignored.

Upvotes: 0

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