CODEWITHSUNDEEP
vhdlghdl
pico
pico

Reputation: 1910

VHDL: bound check error when adding two numbers

Why does this VHDL code cause a bounds check failure? My result signal is 1 bit wider than the widest number being added... thus it shouldn't overflow... Am i missing something?

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity testbench is
end entity;

architecture sim of testbench is
    constant dw       :natural                 := 8;
    signal   arg1     :unsigned(dw-1 downto 0) := to_unsigned(4, dw);       
    signal   result   :unsigned(dw+0 downto 0);
begin
    result <= arg1 + '1';
end architecture;

C:> ghdl -a --std=08 --ieee=synopsys --work=work testbench.vhd

C:> ghdl --elab-run --std=08 --ieee=synopsys testbench --ieee-asserts=disable

ghdl.exe:error: bound check failure at testbench.vhd:13 from: process work.testbench(sim).P0 at testbench.vhd:13

ghdl.exe:error: simulation failed

Upvotes: 2

Views: 4662

Answers (2)

FlyingDodo
FlyingDodo

Reputation: 33

I would like to add a note to @renaud's answer. VHDL is strongly typed language, That is every signal on the both sides of an operator should have exact matching types and sizes. Hence care must be taken in ensuring that the types of all signals you have used in the expression is of same size and type. In your code since you have allocated a extra bit for overflow, you should also change the size of the input signal. This is not a problem in verilog though, It takes care of the mismatch by padding of the bits. Though Frustrating, VHDL is quite helpful in clearing out many bugs before simulation.

Upvotes: 1

Renaud Pacalet
Renaud Pacalet

Reputation: 29050

The vector operand of the addition should have the same length as the target of the assignment. Extend if needed:

result <= ('0' & arg1) + '1';

Upvotes: 4

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