CODEWITHSUNDEEP
vhdl
john7
john7

Reputation: 123

Convert bytes to a std_logic_vector

I have a byte array

type str_t is array(integer range<>) of std_logic_vector(7 downto 0);
signal rx_uart_buf : str_t(0 to RX_BUF_SIZE-1);

I get a number on UART

if (rx_rdy3 = '1') then
    if(RX_DATA > X"2F" and RX_DATA < X"3A") then  
        rx_uart_buf(rx_idx) <= RX_DATA - X"30"; --convert to a number
    else
        rx_uart_buf(rx_idx) <= RX_DATA; 
    end if;

        if (rx_idx < RX_BUF_SIZE-1) then
            rx_idx := rx_idx + 1;
        end if;
end if;

So if it was sent "1234" I have in the buffer

rx_uart_buf(0) - X"01"
rx_uart_buf(1) - X"02"
rx_uart_buf(2) - X"03"
rx_uart_buf(3) - X"04"

How I can convert the bytes to std_logic_vector

signal reg_data : std_logic_vector(15 downto 0) := X"0000";

To get reg_data - X"1234".

Upvotes: 0

Views: 1220

Answers (1)

dalex78
dalex78

Reputation: 238

As other people said, your question is incomplete and does not have a minimal reproductible code. In other word, it is hard to help you.

From point of view, from each bytes in rx_uart_buf, you are taking the 4 lowest significant bits and assignig them into a part of reg_data. You are NOT writing the all byte into reg_data !

To perform this, I am using a for loop: some explanation about the for loop here

optional_label: for parameter in range loop
    sequential statements
end loop label;

It gives me: 

--a for loop that assign the first 4 less significant bits of each bytes of rx_uart_buf into reg_data.
            conversion : for i in rx_uart_buf'reverse_range loop
                reg_data(i*4+3 downto i*4) <= rx_uart_buf(i)(3 downto 0);
            end loop;

I have therefore produce my own code doing what you are looking for. It is for simulation purpose.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL; 


entity test_bytes is

end entity;


architecture Behavioral of test_bytes is

    signal   clk         : std_logic := '1';    --the clock (not used, only to see it in the simulation waves)
    constant period      : time := 8us;         --the clock period
    constant half_period : time := 4us;         --the half period of the clock

    --the variables you have in your code
    constant RX_BUF_SIZE : integer := 4;
    type str_t is array(integer range<>) of std_logic_vector(7 downto 0);
    signal rx_uart_buf : str_t(0 to RX_BUF_SIZE-1) := (0 => X"00", 1 => X"00", 2 => X"00", 3 => X"00");
    signal reg_data : std_logic_vector(15 downto 0) := X"0000";

begin

    --the generation of the clock
    clk <= not clk after half_period;


    --a process that convert the first 4 less significant bits of each bytes of rx_uart_buf into reg_data.
    --it is for simulation purpose, everything might not be synthetisable.
    process_conversion : process

        --a procedure that does the function you are looking for
        procedure conversion_buffer is
        begin
            --a for loop that assign the first 4 less significant bits of each bytes of rx_uart_buf into reg_data.
            conversion : for i in rx_uart_buf'reverse_range loop
                reg_data(i*4+3 downto i*4) <= rx_uart_buf(i)(3 downto 0);
            end loop;
        end procedure;

    begin
        wait for 2*period;

        --we have some values in our buffer
        rx_uart_buf <= (0 => X"01", 1 => X"02", 2 => X"03", 3 => X"04");
        reg_data <= X"0000";
        wait for 1*period;
        --we assign the values into the new signal
        conversion_buffer;
        wait for 2*period;

        --we have some values in our buffer
        rx_uart_buf <= (0 => X"0f", 1 => X"0e", 2 => X"0d", 3 => X"0c");
        reg_data <= X"0000";
        wait for 1*period;
        --we assign the values into the new signal
        conversion_buffer;
        wait for 2*period;

        --we have some values in our buffer
        rx_uart_buf <= (0 => X"10", 1 => X"20", 2 => X"30", 3 => X"40");
        reg_data <= X"0000";
        wait for 1*period;
        --we assign the values into the new signal
        conversion_buffer;
        wait for 2*period;

        --we have some values in our buffer
        rx_uart_buf <= (0 => X"f1", 1 => X"a2", 2 => X"0d", 3 => X"45");
        reg_data <= X"0000";
        wait for 1*period;
        --we assign the values into the new signal
        conversion_buffer;

        wait;
    end process;

end architecture;

If you need other informations, you can edit your post.

Upvotes: 1

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