CODEWITHSUNDEEP
verilogsystem-verilog
Karan Shah
Karan Shah

Reputation: 1992

External Pullup in Systemverilog Interface

I want to model an external pull up in my interface.

interface inter();
  wire a;
  wire a_out;

  assign (pull1, strong0) a = (a_out === 1'b0) ? 1'b0 : 1'b1;
  // assign (pull1, strong0) a = a_out;
  // pullup p1 (a_out);
endinterface

So when a_out is 0, then a should be 0, but when a_out is Z, then a should be pulled up to 1.

Currently I am using === to compare, because primitives don't work in interface.

Is there any better way, as I believe usage of === should be avoided?

Also my main application is to use this net in a class task through virtual interface.

Upvotes: 1

Views: 4823

Answers (1)

dave_59
dave_59

Reputation: 42698

There's no need to do any of this if you simply change the declaration of a_out to

tri1 a_out;

Upvotes: 2

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