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vhdlfpgaclockvivadopwm
Austin Dubes
Austin Dubes

Reputation: 11

VHDL Audio Project

I am trying to attempt a school project on a Nexys 4 DDR board. The project I was interested in is separated in to 2 parts:

  1. Emulating a Vu meter (decibel meter) using the PDM microphone built-in on the board and displaying on the 16 LED's. The louder the sound, the more LED's that light up.

  2. Generating a sound frequency (square wave) from 0 to 32,767 Hz by translating the 15 switches on the board to a 15-bit binary number. I plan to use the PWM audio Output to a speaker to demonstrate.

The remaining switch on the board will be used to toggle between the 2 modes. I am trying to research various projects online, but most are not open-source and have not helped. I am completely lost on how to implement the first part and have a rough idea on how to implement the second part.

For the second part I had planed to use a clock divider to divide 100 MHz clock (Pin E3), but a bit unsure how to do that as well. Ideally, I would like to control the output frequency in 1 Hz increments. For example, out of the 15 switch input, if the least significant bit (lets call it switch[0]) is the only HIGH bit, the output frequency would be 1 Hz. If switch[1] is HIGH, frequency is 2 Hz. If switch[1] and switch[0] are both HIGH, frequency is 3 Hz. And so on..

It should also be said that I am very new to using FPGA's.

Any kind of help would be greatly appreciated!

Upvotes: 0

Views: 833

Answers (1)

wilcroft
wilcroft

Reputation: 1635

If your incoming audio is a simple tone, you can use the magnitude of your audio signal as a measure of loudness; if you have a more complex sounds composed of multiple frequencies, you'll need to perform a FFT first to extract the component waveforms. From there, pick your preferred frequency and use that.

For a PWM, you have two options. The first is to have some counter logic to create a new clock signal. This method is not recommended for creating a clock that is used to control other logic, as it can create significant setup and/or hold violations. The second is to use a PLL/DLL to generate a new clock signal from your previous one. This will be more stable than if you generated it with the configurable logic, and can be used to control other registers if so desired, but will have a limited clock range (typically ~1MHz to 1GHz) it can generate.

The third (and better) is to use your 100MHz clock, but only enable changes at specific time; a pseudocode for this method might be:

Every (1MHz) clock cycle, counter = counter + 1
  If counter = frequency value/2 (i.e. 50,000,00 for 1MHz, 16,666,666 for 3MHz, etc)
     Instead, set counter to 0 and toggle the output signal

This will give you a signal that changes as desired (i.e. twice every second to produce a 1MHz signal), provided you can determine the correct frequency value :)

Upvotes: 1

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