CODEWITHSUNDEEP
veriloggenerate
KEVIN GAJERA
KEVIN GAJERA

Reputation: 21

`define in generate if statement

This generates single bit out, for all values of parameter syn. Why for syn>0 its not generating 2 bit out 

module test
        (clk,
         rst_n,
         en,
         rst_n2,
         in,
         out
         );

parameter syn=0;

generate if(syn>0)begin 
    `define ROMS
end endgenerate

input clk;
input rst_n;
input en;
input rst_n2;



`ifdef ROMS
    input  in;
    output reg  out;
`endif



`ifndef ROMS
    input [1:0] in;
    output reg [1:0] out;
`endif



always_ff@(posedge clk or negedge rst_n or negedge en) begin 
    if(~rst_n) begin 
         out <= 0;
     end else if(clk) begin 
         out <= 0;
     end else if(rst_n2 == 1'b0)begin 
         out <= 0;
     end else begin     
         out <= in;
     end 
end

endmodule

Upvotes: 2

Views: 693

Answers (1)

Matthew
Matthew

Reputation: 13987

Because `define is a compile directive. It is evaluated before your code is compiled. `ROMS is always defined, whatever the value of syn.

Upvotes: 2

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