CODEWITHSUNDEEP
verilogconstantssystem-verilogcompile-time-constant
nikhil bellad
nikhil bellad

Reputation: 1

Constant value in Verilog

How to define a constant value for addition in verilog,

for example if I define a value A=64'h000000000000001;

use it later for addition how should I define in verilog.

Upvotes: -2

Views: 3964

Answers (1)

dave_59
dave_59

Reputation: 42723

In SystemVerilog, it's reccomended that you put all constants in a global package, and import the package where needed

package globals;

  parameter A=64'h000000000000001;

endpackage

Upvotes: 2

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