CODEWITHSUNDEEP
verilogtest-bench
Joshua Ron Garcia
Joshua Ron Garcia

Reputation: 11

Illegal output or input port connection

So this is my test bench.

module testbench;
wire clk;
reg A, B, C, D;
sequential_module sequential_module(.A(A), .B(B), .C(C), .D(D), .clk(clk));
initial
    begin
        $display("Simulating output for Half Subtractor");
        $monitor($time,,," A=%b B=%b C=%b D=%b clk=%b" , A,B,C,D,clk);
        A=1'b0;C=1'b0;D=1'b0; 
        //#1 A=1'b1;B=1'b0;C=1'b0;D=1'b1; 
        //#1 A=1'b1;B=1'b1;C=1'b1;D=1'b0;
        //#2 $finish;
    end
endmodule

This is my module

module sequential_module(A, B, C, D, clk);
input clk;
output A, B, C, D;
reg A, B, C, D;

always @(posedge clk)
begin
   A = B;    //blocking statement 1
   B = A;    //blocking statement 2
end

always @(posedge clk)
begin
   C <= D;   //non-blocking statement 1
   D <= C;   //non-blocking statement 2
end

endmodule

The code is pretty basic but I still can't resolve this problem.

The error (for all 4 ports) : "Error (suppressible): (vsim-3053) Illegal output or inout port connection for port 'A'"

Upvotes: 0

Views: 948

Answers (1)

dave_59
dave_59

Reputation: 42698

You are trying to set variables that are driven by the output of another module. You cannot do that in Verilog (or SystemVerilog). Also, Verilog only lets connect outputs to wires. If you are just experimenting, you can use hierarchical references to do that.

module testbench;
wire clk;
wire A, B, C, D;
sequential_module s_m(.A(A), .B(B), .C(C), .D(D), .clk(clk));
initial
    begin
        $display("Simulating output for Half Subtractor");
        $monitor($time,,," A=%b B=%b C=%b D=%b clk=%b" , A,B,C,D,clk);
        s_m.A=1'b0;s_m.C=1'b0;s_m.D=1'b0; 
        //#1 A=1'b1;B=1'b0;C=1'b0;D=1'b1; 
        //#1 A=1'b1;B=1'b1;C=1'b1;D=1'b0;
        //#2 $finish;
    end
endmodule

But real hardware does not have hierarchical references; everything must be connected through ports. You would have to add another set of 4 inputs, plus another LOAD signal.

module sequential_module(output reg A, B, C, D, input wire clk,
                         input wire Ain, Bin, Cin, Din, LOAD);
always @(posedge clk)
if (LOAD) begin
   A = Ain;
   B = Bin;
end else begin
   A = B;    //blocking statement 1
   B = A;    //blocking statement 2
end

always @(posedge clk)
if (LOAD) begin
   C <= Cin;
   D <= Din;
end else begin
   C <= D;   //non-blocking statement 1
   D <= C;   //non-blocking statement 2
end

endmodule

Upvotes: -1

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