CODEWITHSUNDEEP
verilogfpgamodelsim
yeongck
yeongck

Reputation: 11

How can I run this Verilog module sequentially?

I want to make a testbench run sequentially. What I'm expecting is running AES_input at first and after it finishes, the second module AES_TOP runs. I made a parameter i_out1, and if AES_input i_out become 0 to 1, then the second module run

I checked it compiled successfully but I found out it's illegal connection. I don't know how I solve this problem. Is there any other way to run these module sequentially?

`timescale 1ns / 1ps

module AES_TB;

// Inputs
reg clk;

parameter i_out1 = 1'b0;
wire [258943:0] p_out;
wire a_out;
wire [258943:0] dataout;




AES_input t1 (.p_out(p_out), .i_out(i_out1));

generate if(i_out1 == 1)begin : ci
    AES_TOP t2 (
        .clk(clk), .p(p_out),
        .dataout(dataout),.a_out(a_out));

end
endgenerate



AES_output t3 (.dataout(dataout), .a_out(a_out));



endmodule

Upvotes: 0

Views: 1078

Answers (3)

Joe
Joe

Reputation: 1031

HDLs allow you to create structures that operate concurrently - the structure exists, and the only sequential nature is in the data that is passed to it. Below I have added a clock source so that your internal logic can have a clock for sequential processing, and also added an initial statement, so you can sequentially change input values. Your blocks appear to have no inputs - most blocks in HDLs are transfer functions - some function operating on a set of inputs to produce an output. I removed the generate statements - start first with three instances, and connect them the way you want. Then if you need more after it's working, then add the generate statements.

`timescale 1ns / 1ps

module AES_TB;

// Inputs
reg clk=0; //initialize clock, otherwise you will just have x's (red)
always #4 clk=!clk; // define clock function

parameter i_out1 = 1'b0;
wire [258943:0] p_out;
wire a_out;
wire [258943:0] dataout;

reg i0, i1, i2;
initial begin // this creates sequential vector assignment
  i0=0; // initialize values
  i1=0;
  i2=0;
  #5;
  i0=1;//after some time, assign values
  i1=1;
  i2=1;
  @(posedge clk);
  i0=0;//after clock, assign values
  i1=0;
  i2=0;



end


AES_input t1 (
   .some_control_input(i0),
   .p_out(p_out), 
   .i_out(i_out1));
AES_input t2 (
   .some_control_input(i1),
   .p_out(i_out1), 
   .i_out(i_out2));
AES_output t3 (
   .some_control_input(i2),
   .dataout(dataout), 
   .a_out(a_out)
);



endmodule

Upvotes: 0

Serge
Serge

Reputation: 12364

Verilog is a "hardware description language", it is not a generic programming language. As such, it allow description of the structure of hardware systems. There is nothing sequential in hardware itself. It is massively parallel. The result of the hardware evaluation depends on the input signals, connections between elements and the previous state.

Verilog tries to mimic hardware behavior by providing hardware modules. Modules describe hardware hierarchy by hierarchy of instances and nothing else. They cannot be 'executed' nor can they be execute in a 'sequence'. Module instances are connected with each other by "wires" which transfer signal values.

Module itself is described in terms of continuous assignments and procedural blocks, e.g., 'always' blocks. They describe connections inside modules and low level hardware devices. They are also connected by a set of wires inside the module. The only sequential programming piece in verilog exist within procedural blocks which describe behavior of hardware devices.

In order to simulate parallel behavior of hardware verilog employs event-driven technique. This means that a certain procedural block gets evaluated if and only if at least one of its input's value changes. As a result, sequence of evaluation of device models depends on the values of the signals in the model. Modules are only containers for those device models and are never evaluated as a whole.

In your case you instantiate a few modules multiple times passing the same wire as an output wire. Verilog is very picky about how such wires are evaluated. Most likely you got 'x' on such wires in your case. The reason is that verilog evaluates them according to the above rules and figures out that the same wire is driven by multiple devices with different values. In parallel hardware world it has no idea which value is correct, therefore it puts 'x' there.

In order to describe a sequence of assignments in verilog you need to provide more wires to do so, for example

     wire in, out[3];
     moda mod1(.in(in), .out(out[0]);
     modb mod2(.in(out[0]), .out(out[1]));
     modc mod3(.in(out[1]), .out(out[2]));
     
     ...

This way you can use 'in' as a stimulus input and out[2] as a wire of interest for your test bench.

Upvotes: 1

Anusha Manoj
Anusha Manoj

Reputation: 19

Basically you cannot have a sequential run of modules in Digital system design. All of them are executed parallelly. In a logic gates env, you cannot have one by one getting executed.

But here in this case, what you can do is to have a enable and finish signal for each of the module. So for the first module, you can provide the enable from the testbench, then for the next modules, tie the enable to finish signal of the previous. That way you can manage a cascaded execution.

Upvotes: -1

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